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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 114...	Line 114...






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`








`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.rx.sim`	`uart_rx`


`dest_dir`
`../verilog`





Line 158...	Line 138...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.rx.syn`	`uart_rx`


`dest_dir`
`../verilog`





Line 188...	Line 164...





`../verilog/sim/top.rx.sim`	`../verilog/sim/uart_rx`
`verilogSourcemodule`	`verilogSourcemodule`




Line 205...	Line 181...
`../verilog/top.sim`	`../verilog/top.sim`
`verilogSourcefragment`	`verilogSourcefragment`




	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`








Line 221...	Line 204...





`../verilog/syn/top.rx.syn`	`../verilog/syn/uart_rx`
`verilogSourcemodule`	`verilogSourcemodule`




`../verilog/top.body`	`../verilog/top.body`
`verilogSourcefragment`	`verilogSourcefragment`




	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`









Line 313...	Line 304...








`PRESCALE5'b01100`
`PRE_SIZE5`
`SIZE8`
`DIV0`
`DIV_SIZE4`
`RX_FIFO_SIZE3`
`RX_FIFO_WORDS8`







`parity_enable`	`parity_enable`
`wire`	`wire`
`in`	`in`

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