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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 112...	Line 112...






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`







`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
Line 137...	Line 123...
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.tx.sim`	`uart_tx`


`dest_dir`
`../verilog`





Line 155...	Line 137...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.tx.syn`	`uart_tx`


`dest_dir`
`../verilog`





Line 183...	Line 161...





`../verilog/sim/top.tx.sim`	`../verilog/sim/uart_tx`
`verilogSourcemodule`	`verilogSourcemodule`




Line 199...	Line 177...

`../verilog/top.sim`	`../verilog/top.sim`
`verilogSourcefragment`	`verilogSourcefragment`



	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`







Line 215...	Line 199...





`../verilog/syn/top.tx.syn`	`../verilog/syn/uart_tx`
`verilogSourcemodule`	`verilogSourcemodule`




`../verilog/top.body.tx`	`../verilog/top.body.tx`
`verilogSourcefragment`	`verilogSourcefragment`



	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`







Line 309...	Line 299...






`PRESCALE5'b01100`
`PRE_SIZE5`
`SIZE8`
`DIV0`
`DIV_SIZE4`
`TX_FIFO_SIZE3`
`TX_FIFO_WORDS8`








`parity_enable`	`parity_enable`

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