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Line 25... |
// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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uart
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uart
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rx_tb
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rx_tb
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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:*common:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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uart_rx_tb
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uart_rx_tb
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UART_MODEL_CLKCNT4'hc
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UART_MODEL_CLKCNT4'hc
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UART_MODEL_SIZE4
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UART_MODEL_SIZE4
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DIVIDER4'b0000
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DIVIDER4'b0000
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Params
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Params
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spirit:library="logic"
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ipxact:library="logic"
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spirit:name="uart"
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ipxact:name="uart"
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spirit:version="rx_dut.params"/>
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ipxact:version="rx_dut.params"/>
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Bfm
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Bfm
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spirit:library="logic"
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ipxact:library="logic"
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spirit:name="uart"
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ipxact:name="uart"
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spirit:version="bfm.design"/>
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ipxact:version="bfm.design"/>
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icarus
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icarus
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spirit:library="Testbench"
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ipxact:library="Testbench"
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spirit:name="toolflow"
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ipxact:name="toolflow"
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spirit:version="icarus"/>
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ipxact:version="icarus"/>
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commoncommon
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common:*common:*
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Verilog
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Verilog
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fs-common
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fs-common
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sim:*Simulation:*
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sim:*Simulation:*
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Verilog
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Verilog
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fs-sim
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fs-sim
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lint:*Lint:*
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lint:*Lint:*
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Verilog
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Verilog
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fs-lint
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fs-lint
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fs-common
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fs-common
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../verilog/tb.ext
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../verilog/tb.ext
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verilogSourcefragment
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verilogSourcefragment
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fs-sim
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fs-sim
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../verilog/common/uart_rx_tb
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../verilog/common/uart_rx_tb
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verilogSourcemodule
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verilogSourcemodule
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fs-lint
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fs-lint
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../verilog/common/uart_rx_tb
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../verilog/common/uart_rx_tb
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verilogSourcemodule
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verilogSourcemodule
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