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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rxtx_tb.xml] - Diff between revs 131 and 134

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Rev 131 Rev 134
Line 52... Line 52...
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
  
  
    
    
      destination
      destination
      top.rxtx_tb
      uart_rxtx_tb
    
 
    
 
      dest_dir
 
      ../verilog
 
    
 
    
 
      top
 
    
    
  
  
 
 
 
 
 
 
Line 174... Line 167...
    
    
      fs-sim
      fs-sim
 
 
      
      
        
        
        ../verilog/common/top.rxtx_tb
        ../verilog/common/uart_rxtx_tb
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
    
    
 
 
Line 187... Line 180...
    
    
      fs-lint
      fs-lint
 
 
      
      
        
        
        ../verilog/common/top.rxtx_tb
        ../verilog/common/uart_rxtx_tb
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
    
    
 
 

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