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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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usb_epp
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usb_epp
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def default
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def
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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slave_reset
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reset
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reset
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reset
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reset
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gen_verilog
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104.0
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none
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common
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./tools/verilog/gen_verilog
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destination
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usb_epp_def
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gen_verilog
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104.0
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none
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:*common:*
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tools/verilog/gen_verilog
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destination
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usb_epp_def
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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verilog
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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commoncommon
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Verilog
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fs-common
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common:*common:*
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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sim:*Simulation:*
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Verilog
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Verilog
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fs-syn
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fs-sim
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syn:*Synthesis:*
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Verilog
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doc
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fs-syn
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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eppastb_in
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wire
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in
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eppdstb_in
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wire
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in
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usbflag_in
|
clk
|
wire
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wire
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in
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in
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eppwait_out
|
reset
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wire
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wire
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out
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in
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eppwait_in
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wire
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in
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eppwait_oe
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wire
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out
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usbwr_out
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eppastb_in
|
wire
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wire
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out
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in
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usbwr_oe
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eppdstb_in
|
wire
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wire
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out
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in
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usbwr_in
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usbflag_in
|
wire
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wire
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in
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in
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usbmode_out
|
eppwait_out
|
wire
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wire
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out
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out
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usbmode_oe
|
eppwait_in
|
wire
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wire
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out
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in
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usbmode_in
|
eppwait_oe
|
wire
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wire
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in
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out
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usboe_out
|
usbwr_out
|
wire
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wire
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out
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out
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usboe_oe
|
usbwr_oe
|
wire
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wire
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out
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out
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usboe_in
|
usbwr_in
|
wire
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wire
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in
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in
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usbadr_out
|
usbmode_out
|
wire
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wire
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out
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out
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10
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usbadr_oe
|
usbmode_oe
|
wire
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wire
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out
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out
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usbadr_in
|
usbmode_in
|
wire
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wire
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in
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in
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10
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usbpktend_out
|
usboe_out
|
wire
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wire
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out
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out
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usbpktend_oe
|
usboe_oe
|
wire
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wire
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out
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out
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usbpktend_in
|
usboe_in
|
wire
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wire
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in
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in
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usbdir_out
|
usbadr_out
|
wire
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wire
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out
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out
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10
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usbdir_oe
|
usbadr_oe
|
wire
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wire
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out
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out
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usbdir_in
|
usbadr_in
|
wire
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wire
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in
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in
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10
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eppdb_in
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usbpktend_out
|
wire
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wire
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in
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out
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70
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eppdb_out
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usbpktend_oe
|
wire
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wire
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out
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out
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70
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eppdb_oe
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usbpktend_in
|
wire
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wire
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out
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in
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eppwr_in
|
usbdir_out
|
wire
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wire
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in
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out
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usbclk_out
|
usbdir_oe
|
wire
|
wire
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out
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out
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usbclk_oe
|
usbdir_in
|
wire
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wire
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out
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in
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usbclk_in
|
eppdb_in
|
wire
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wire
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in
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in
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70
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usbrdy_in
|
eppdb_out
|
wire
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wire
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in
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out
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70
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eppdb_oe
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wire
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out
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eppwr_in
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wire
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in
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usbclk_out
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wire
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out
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usbclk_oe
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wire
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out
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usbclk_in
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wire
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in
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usbrdy_in
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wire
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in
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fs-common
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../verilog/top.body
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|
verilogSourcefragment
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fs-common
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../verilog/top.body
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verilogSourcefragment
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fs-sim
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/usb_epp_def
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|
verilogSourcemodule
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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fs-sim
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|
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../verilog/copyright
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verilogSourceinclude
|
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../verilog/common/usb_epp_def
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|
verilogSourcemodule
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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fs-syn
|
|
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../verilog/copyright
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verilogSourceinclude
|
|
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../verilog/common/usb_epp_def
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|
verilogSourcemodule
|
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dest_dir
|
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../views/syn/
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verilogSourcelibraryDir
|
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fs-syn
|
|
|
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../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
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../verilog/common/usb_epp_def
|
|
verilogSourcemodule
|
|
|
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dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
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