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URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Diff between revs 133 and 134

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Rev 133 Rev 134
Line 71... Line 71...
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
  102.1
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
  104.0
  104.0
  none
  none
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
  
  
    
    
      destination
      destination
      top
      usb_epp_def
    
 
    
 
      dest_dir
 
      ../verilog
 
    
    
  
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
    
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/top.body
 
        verilogSourcefragment
 
      
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
    
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright.v
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/top
 
        verilogSourcemodule
 
      
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
    
 
      fs-syn
 
 
 
      
 
        
 
        ../verilog/copyright.v
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/top
 
        verilogSourcemodule
 
      
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
       
       
 
 
              
              
              verilog
              verilog
Line 424... Line 335...
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
    
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/top.body
 
        verilogSourcefragment
 
      
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
    
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/usb_epp_def
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
      
 
        dest_dir
 
        ../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
    
 
      fs-syn
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/usb_epp_def
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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