URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [top.body] - Diff between revs 131 and 134

Rev 131	Rev 134
Line 28...	Line 28...
`#(.H_ACTIVE(H_ACTIVE))`	`#(.H_ACTIVE(H_ACTIVE))`
`CHAR_DISPLAY`	`CHAR_DISPLAY`
`(`	`(`
`.clk ( clk ),`	`.clk ( clk ),`
`.reset ( reset ),`	`.reset ( reset ),`
`.char_column ( char_column ),`
`.char_line ( char_line ),`
`.subchar_line ( subchar_line ),`	`.subchar_line ( subchar_line ),`
`.subchar_pixel ( subchar_pixel ),`	`.subchar_pixel ( subchar_pixel ),`
`.pixel_on ( pixel_on ),`	`.pixel_on ( pixel_on ),`
`.char_read_addr ( char_read_addr),`	`.char_read_addr ( char_read_addr),`
`.char_write_addr ( address ),`	`.char_write_addr ( address ),`
`.char_write_data ( wdata ),`	`.char_write_data ( wdata ),`
	`.char_gen_rom_data ( char_gen_rom_data ),`
`.char_write_enable ( ascii_load ),`	`.char_write_enable ( ascii_load ),`
`.ascii_code ( ascii_code )`	`.ascii_code ( ascii_code )`

`);`	`);`

Line 109...	Line 108...
`if(add_h_load) address[13:8] <= wdata[5:0];`	`if(add_h_load) address[13:8] <= wdata[5:0];`
`else`	`else`
`if(ascii_load) address <= address+ 14'b0000000000001;`	`if(ascii_load) address <= address+ 14'b0000000000001;`
`else address <= address;`	`else address <= address;`

	`always @ (*)`
	`begin`
	`char_read_addr = (char_line[6:0] * H_ACTIVE / 8 ) + {7'b0000000,char_column[6:0]};`
	`end`


	`assign chargen_rom_address = {ascii_code[7:0], subchar_line[2:0]};`
`No newline at end of file`	`No newline at end of file`