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Line 25... |
// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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vga_char_ctrl
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vga_char_ctrl
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def default
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def
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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slave_reset
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reset
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reset
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reset
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reset
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vga
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vga
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hsync_n_pad_out
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hsync_n_pad_out
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vsync_n_pad_out
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hsync_n_pad_out
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vsync_n_pad_out
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hsync_n_pad_out
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vsync_n_pad_out
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vsync_n_pad_out
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red_pad_out
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red_pad_out
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20
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red_pad_out
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red_pad_out
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20
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green_pad_out
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green_pad_out
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20
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green_pad_out
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green_pad_out
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20
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blue_pad_out
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blue_pad_out
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10
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blue_pad_out
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blue_pad_out
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10
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gen_verilog
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104.0
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none
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common
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./tools/verilog/gen_verilog
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destination
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vga_char_ctrl_def
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gen_verilog
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104.0
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none
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:*common:*
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tools/verilog/gen_verilog
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destination
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vga_char_ctrl_def
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fs-common
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../verilog/top.body
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verilogSourcefragment
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fs-sim
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fs-common
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../verilog/copyright
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../verilog/top.body
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verilogSourceinclude
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verilogSourcefragment
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../verilog/common/vga_char_ctrl_def
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verilogSourcemodule
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char_display
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../verilog/char_display
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verilogSourcemodule
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char_gen
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../verilog/char_gen
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verilogSourcemodule
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svga_timing_generation
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fs-sim
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../verilog/svga_timing_generation
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verilogSourcemodule
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video_out
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../verilog/video_out
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../verilog/copyright
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verilogSourcemodule
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verilogSourceinclude
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../verilog/common/vga_char_ctrl_def
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verilogSourcemodule
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char_display
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../verilog/char_display
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verilogSourcemodule
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dest_dir
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char_gen
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../views/sim/
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../verilog/char_gen
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verilogSourcelibraryDir
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verilogSourcemodule
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svga_timing_generation
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../verilog/svga_timing_generation
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verilogSourcemodule
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video_out
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../verilog/video_out
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verilogSourcemodule
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fs-syn
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/vga_char_ctrl_def
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verilogSourcemodule
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char_display
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../verilog/char_display
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verilogSourcemodule
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char_gen
|
fs-syn
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../verilog/char_gen
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verilogSourcemodule
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svga_timing_generation
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../verilog/svga_timing_generation
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verilogSourcemodule
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video_out
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../verilog/video_out
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../verilog/copyright
|
verilogSourcemodule
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verilogSourceinclude
|
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../verilog/common/vga_char_ctrl_def
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verilogSourcemodule
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char_display
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../verilog/char_display
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verilogSourcemodule
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dest_dir
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char_gen
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../views/syn/
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../verilog/char_gen
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verilogSourcelibraryDir
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verilogSourcemodule
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svga_timing_generation
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../verilog/svga_timing_generation
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verilogSourcemodule
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video_out
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../verilog/video_out
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verilogSourcemodule
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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Hierarchical
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spirit:library="logic"
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spirit:name="vga_char_ctrl"
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spirit:version="def.design"/>
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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commoncommon
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
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Hierarchical
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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Hierarchical
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Hierarchical
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doc
|
verilog
|
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spirit:library="Testbench"
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ipxact:library="Testbench"
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spirit:name="toolflow"
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ipxact:name="toolflow"
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spirit:version="documentation"/>
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ipxact:version="verilog"/>
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:*Documentation:*
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Verilog
|
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common:*common:*
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
|
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fs-sim
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CHARACTER_DECODE_DELAY4
|
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H_ACTIVE640
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V_ACTIVE480
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H_FRONT_PORCH16
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H_SYNCH96
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H_BACK_PORCH48
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H_TOTAL800
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V_FRONT_PORCH11
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V_SYNCH2
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V_BACK_PORCH31
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V_TOTAL524
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CHAR_RAM_ADDR13
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CHAR_RAM_WIDTH8
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CHAR_RAM_WORDS4800
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CHAR_RAM_WRITETHRU0
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syn:*Synthesis:*
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Verilog
|
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fs-syn
|
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ascii_load
|
|
wire
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doc
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in
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|
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|
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ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
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|
|
:*Documentation:*
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|
Verilog
|
|
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add_l_load
|
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wire
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in
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add_h_load
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wire
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in
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wdata
|
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wire
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in
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70
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address
|
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reg
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out
|
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130
|
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char_color
|
|
wire
|
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in
|
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70
|
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back_color
|
|
wire
|
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in
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70
|
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cursor_color
|
clk
|
wire
|
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in
|
wire
|
70
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in
|
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reset
|
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wire
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in
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hsync_n_pad_out
|
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wire
|
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out
|
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vsync_n_pad_out
|
|
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|
wire
|
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out
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red_pad_out
|
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wire
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out
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green_pad_out
|
|
|
|
wire
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out
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blue_pad_out
|
|
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|
wire
|
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out
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ascii_load
|
|
|
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wire
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in
|
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add_l_load
|
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wire
|
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in
|
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add_h_load
|
|
wire
|
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in
|
|
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|
wdata
|
|
wire
|
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in
|
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70
|
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|
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|
address
|
|
reg
|
|
out
|
|
130
|
|
|
|
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|
char_color
|
|
wire
|
|
in
|
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70
|
|
|
|
|
|
back_color
|
|
wire
|
|
in
|
|
70
|
|
|
|
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|
cursor_color
|
|
wire
|
|
in
|
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70
|
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