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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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wishbone
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wishbone
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wb
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wb
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b.2_rtl
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b.2_rtl
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clk
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clk
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The clock input coordinates all activities for the internal logic within the WISHBONE interconnect. All WISHBONE output signals are registered at the rising edge of clk. All WISHBONE input signals are stable before the rising edge of clk.
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The clock input coordinates all activities for the internal logic within the WISHBONE interconnect. All WISHBONE output signals are registered at the rising edge of clk. All WISHBONE input signals are stable before the rising edge of clk.
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true
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true
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CLOCK
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CLOCK
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required
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required
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1
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1
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out
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out
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RESET
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RESET
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optional
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optional
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1
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1
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out
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out
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required
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required
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1
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1
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in
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in
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required
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required
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1
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1
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in
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in
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true
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true
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enable
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enable
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The enable input determines if a clk cycle should be acted upon or ignored for all operations including reset.
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The enable input determines if a clk cycle should be acted upon or ignored for all operations including reset.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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required
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required
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1
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1
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out
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out
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optional
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optional
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1
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1
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in
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in
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optional
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optional
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1
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1
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in
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in
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rst
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rst
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The rst input forces the WISHBONE interface to restart. Furthermore, all internal self-starting state machines will be forced into an initial state. This signal only resets the WISHBONE interface. It is not required to reset other parts of an IP core (although it may be used that way).
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The rst input forces the WISHBONE interface to restart. Furthermore, all internal self-starting state machines will be forced into an initial state. This signal only resets the WISHBONE interface. It is not required to reset other parts of an IP core (although it may be used that way).
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true
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true
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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required
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required
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1
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1
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out
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out
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required
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required
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1
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1
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in
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in
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required
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required
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1
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1
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in
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in
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true
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true
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adr
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adr
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The adr output array is used to pass a binary address. The higher array boundary is specific to the address width of the core, and the lower array boundary is determined by the data port size and granularity. For example the array size on a 32-bit data port with BYTE granularity is adr[n:2]. In some cases (such as FIFO interfaces) the array may not be present on the interface.
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The adr output array is used to pass a binary address. The higher array boundary is specific to the address width of the core, and the lower array boundary is determined by the data port size and granularity. For example the array size on a 32-bit data port with BYTE granularity is adr[n:2]. In some cases (such as FIFO interfaces) the array may not be present on the interface.
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true
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true
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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out
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out
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required
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required
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in
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in
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cyc
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cyc
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The cycle output when asserted, indicates that a valid bus cycle is in progress. The signal is asserted for the duration of all bus cycles. For example, during a BLOCK transfer cycle there can be multiple data transfers. The signal is asserted during the first data transfer, and remains asserted until the last data transfer. The signal is useful for interfaces with multi-port interfaces (such as dual port memories). In these cases, the signal requests use of a common bus from an arbiter.
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The cycle output when asserted, indicates that a valid bus cycle is in progress. The signal is asserted for the duration of all bus cycles. For example, during a BLOCK transfer cycle there can be multiple data transfers. The signal is asserted during the first data transfer, and remains asserted until the last data transfer. The signal is useful for interfaces with multi-port interfaces (such as dual port memories). In these cases, the signal requests use of a common bus from an arbiter.
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true
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true
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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out
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out
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required
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required
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in
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in
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wdata
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wdata
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The data output array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. wdata[63:0].Also see the rdata[] and sel[] signal descriptions.
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The data output array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. wdata[63:0].Also see the rdata[] and sel[] signal descriptions.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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out
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out
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required
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required
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in
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in
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rdata
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rdata
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The data input array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. rdata[63:0]. Also see the wdata[] and sel[] signal descriptions.
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The data input array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. rdata[63:0]. Also see the wdata[] and sel[] signal descriptions.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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in
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in
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required
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required
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out
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out
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ack
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ack
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The acknowledge input when asserted, indicates the normal termination of a bus cycle. Also see the err and rty signal descriptions.
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The acknowledge input when asserted, indicates the normal termination of a bus cycle. Also see the err and rty signal descriptions.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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in
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in
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required
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required
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out
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out
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err
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err
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The error input indicates an abnormal cycle termination. The source of the error, and the response generated by the MASTER is defined by the IP core supplier. Also see the ack and rty signal descriptions.
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The error input indicates an abnormal cycle termination. The source of the error, and the response generated by the MASTER is defined by the IP core supplier. Also see the ack and rty signal descriptions.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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in
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in
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required
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required
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out
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out
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rty
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rty
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The retry input indicates that the interface is not ready to accept or send data, and that the cycle should be retried. When and how the cycle is retried is defined by the IP core supplier. Also see the ack and err signal descriptions.
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The retry input indicates that the interface is not ready to accept or send data, and that the cycle should be retried. When and how the cycle is retried is defined by the IP core supplier. Also see the ack and err signal descriptions.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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in
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in
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required
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required
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out
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out
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sel
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sel
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The select output array indicates where valid data is expected on the rdata signal array during READ cycles, and where it is placed on the wdata signal array during WRITE cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit granularity is used on a 64-bit port, then there would be an array of eight select signals with boundaries of sel[7:0]. Each individual select signal correlates to one of eight active bytes on the 64-bit data port. For more information about sel, please refer to the data organization section in Chapter 3 of this specification. Also see the rdata[], wdata[] and stb signal descriptions.
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The select output array indicates where valid data is expected on the rdata signal array during READ cycles, and where it is placed on the wdata signal array during WRITE cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit granularity is used on a 64-bit port, then there would be an array of eight select signals with boundaries of sel[7:0]. Each individual select signal correlates to one of eight active bytes on the 64-bit data port. For more information about sel, please refer to the data organization section in Chapter 3 of this specification. Also see the rdata[], wdata[] and stb signal descriptions.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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out
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out
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required
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required
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in
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in
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stb
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stb
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The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface such as sel[]. The SLAVE asserts either the ack, err or rty signals in response to every assertion of the stb signal.
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The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface such as sel[]. The SLAVE asserts either the ack, err or rty signals in response to every assertion of the stb signal.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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out
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out
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required
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required
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in
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in
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tagn_i
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tagn_i
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The tag input(s) are user defined, and are used with either MASTER or SLAVE interfaces. ‘N’ in this signal name refers to a tag number because multiple tags may be used (e.g. TAG_I[3]). Tag inputs are used whenever an IP core needs specific information from the interconnection. For example, a MASTER can be designed to monitor the state of a FIFO.
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The tag input(s) are user defined, and are used with either MASTER or SLAVE interfaces. ‘N’ in this signal name refers to a tag number because multiple tags may be used (e.g. TAG_I[3]). Tag inputs are used whenever an IP core needs specific information from the interconnection. For example, a MASTER can be designed to monitor the state of a FIFO.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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in
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in
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required
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required
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out
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out
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tagn_o
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tagn_o
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The tag output(s) are user defined, and are used with either MASTER or SLAVE interfaces. For example, the tag output(s) can be used to indicate the type of data transfer in progress. Furthermore, ‘N’ in this signal name refers to a tag number because multiple tags may be used. For example, tagn_o[1] may indicate a valid data transfer cycle, tagn_o[2] may indicate an interrupt acknowledge cycle and so on. The exact meaning of each tag is defined by the IP core provider in the WISHBONE DATASHEET.
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The tag output(s) are user defined, and are used with either MASTER or SLAVE interfaces. For example, the tag output(s) can be used to indicate the type of data transfer in progress. Furthermore, ‘N’ in this signal name refers to a tag number because multiple tags may be used. For example, tagn_o[1] may indicate a valid data transfer cycle, tagn_o[2] may indicate an interrupt acknowledge cycle and so on. The exact meaning of each tag is defined by the IP core provider in the WISHBONE DATASHEET.
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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out
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out
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required
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required
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in
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in
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we
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we
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The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.
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The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.
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true
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true
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CLOCK
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CLOCK
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illegal
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illegal
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ENABLE
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ENABLE
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illegal
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illegal
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RESET
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RESET
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illegal
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illegal
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required
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required
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out
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out
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required
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required
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in
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in
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