URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_master.xml] - Diff between revs 131 and 134

Rev 131	Rev 134
Line 52...	Line 52...


`adr`	`adr`

`adr`	`adr`
`wb_addr_width-10`	`awidth-10`





`wdata`	`wdata`

`dout`	`dout`
`wb_data_width-10`	`dwidth-10`





`rdata`	`rdata`

`din`	`din`
`wb_data_width-10`	`dwidth-10`





Line 130...	Line 130...











	`gen_verilog_sim`
	`104.0`
	`none`
	`:Simulation:`
	`./tools/verilog/gen_verilog`


	`destination`
	`model_master`






`fs-sim`


`dest_dir../verilog/sim/`	`gen_verilog_syn`
`verilogSourcelibraryDir`	`104.0`
	`none`
	`:Synthesis:`
	`./tools/verilog/gen_verilog`


	`destination`
	`model_master`







`fs-syn`



`dest_dir../verilog/syn/`
`verilogSourcelibraryDir`

















	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`







	`sim:Simulation:`
	`Verilog`


	`fs-sim`




	`syn:Synthesis:`
	`Verilog`


	`fs-syn`








	`doc`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="documentation"/>`

	`:Documentation:`
	`Verilog`





















Line 256...	Line 332...









	`fs-sim`



	`../verilog/sim/master`
	`verilogSourcefragment`





	`../verilog/sim/master.tasks`
	`verilogSourcefragment`





	`../verilog/master_copyright`
	`verilogSourceinclude`





	`../verilog/sim/model_master`
	`verilogSourcemodule`




	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`







	`fs-syn`










	`../verilog/sim/master`
	`verilogSourcefragment`





	`../verilog/sim/master.tasks`
	`verilogSourcefragment`





	`../verilog/master_copyright`
	`verilogSourceinclude`





	`../verilog/sim/model_master`
	`verilogSourcemodule`




	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`