| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
wishbone
|
wishbone
|
model
|
model
|
master default
|
master
|
|
|
|
|
|
|
|
|
|
|
|
|
wb
|
wb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
adr
|
adr
|
|
|
adr
|
adr
|
awidth-10
|
awidth-10
|
|
|
|
|
|
|
|
|
|
|
wdata
|
wdata
|
|
|
dout
|
dout
|
dwidth-10
|
dwidth-10
|
|
|
|
|
|
|
|
|
|
|
rdata
|
rdata
|
|
|
din
|
din
|
dwidth-10
|
dwidth-10
|
|
|
|
|
|
|
|
|
|
|
sel
|
sel
|
|
|
sel
|
sel
|
|
|
|
|
|
|
|
|
|
|
ack
|
ack
|
|
|
ack
|
ack
|
|
|
|
|
|
|
|
|
|
|
cyc
|
cyc
|
|
|
cyc
|
cyc
|
|
|
|
|
|
|
|
|
|
|
|
|
stb
|
stb
|
|
|
stb
|
stb
|
|
|
|
|
|
|
|
|
|
|
we
|
we
|
|
|
we
|
we
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_sim
|
|
104.0
|
|
none
|
|
:*Simulation:*
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
model_master
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_sim
|
|
104.0
|
|
none
|
|
:*Simulation:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
model_master
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_syn
|
|
104.0
|
|
none
|
|
:*Synthesis:*
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
model_master
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_syn
|
|
104.0
|
|
none
|
|
:*Synthesis:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
model_master
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
verilog
|
|
model_master
|
|
|
|
|
|
awidth
|
|
32
|
|
|
|
|
|
dwidth
|
|
32
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
rtl
|
Verilog
|
verilog:Kactus2:
|
|
verilog
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
sim:*Simulation:*
|
|
Verilog
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
fs-sim
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
dwidth32
|
|
awidth32
|
|
|
|
|
|
|
|
|
|
clk
|
|
wire
|
|
in
|
|
|
|
|
|
reset
|
|
wire
|
|
in
|
|
|
|
|
|
adr
|
|
reg
|
|
out
|
|
awidth-10
|
|
|
|
|
|
|
|
dout
|
|
reg
|
dwidth32
|
out
|
awidth32
|
dwidth0
|
|
|
|
|
|
|
|
|
|
cyc
|
clk
|
reg
|
wire
|
out
|
in
|
|
|
|
|
stb
|
reset
|
reg
|
wire
|
out
|
in
|
|
|
|
|
we
|
adr
|
reg
|
reg
|
out
|
out
|
|
awidth-10
|
|
|
|
|
|
|
sel
|
dout
|
reg
|
reg
|
out
|
out
|
dwidth/8-10
|
dwidth0
|
|
|
|
|
|
|
din
|
cyc
|
wire
|
reg
|
in
|
out
|
dwidth-10
|
|
|
|
|
|
|
stb
|
|
reg
|
|
out
|
|
|
|
|
ack
|
we
|
wire
|
reg
|
in
|
out
|
|
|
|
|
err
|
|
wire
|
|
in
|
|
|
|
|
|
rty
|
sel
|
wire
|
reg
|
in
|
out
|
|
dwidth/8-10
|
|
|
|
|
|
|
|
din
|
|
wire
|
|
in
|
|
dwidth-10
|
|
|
|
|
|
|
|
|
|
ack
|
|
wire
|
|
in
|
|
|
|
|
|
err
|
|
wire
|
|
in
|
|
|
|
|
|
rty
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/sim/master
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/sim/master.tasks
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/master_copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
../verilog/sim/model_master
|
../verilog/sim/master
|
verilogSourcemodule
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
dest_dir../views/sim/
|
|
verilogSourcelibraryDir
|
../verilog/sim/master.tasks
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/master_copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
../verilog/sim/model_master
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
../verilog/sim/master
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/sim/master.tasks
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/master_copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/sim/model_master
|
../verilog/sim/master
|
verilogSourcemodule
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
dest_dir../views/sim/
|
|
verilogSourcelibraryDir
|
../verilog/sim/master.tasks
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/master_copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/sim/model_master
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
