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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 158...	Line 158...






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`








`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
Line 184...	Line 169...
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top`	`wb_memory_def`


`dest_dir`
`../verilog`





Line 201...	Line 182...









`fs-common`




`../verilog/top.body`
`verilogSourcefragment`







`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/common/top`
`verilogSourcemodule`









`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/common/top`
`verilogSourcemodule`















Line 351...	Line 271...

`wb_addr_width24`	`wb_addr_width24`
`wb_data_width32`	`wb_data_width32`
`wb_byte_lanes4`	`wb_byte_lanes4`
`dat_width32`	`dat_width32`
`adr_width12`	`adr_width14`
`mem_size16384`	`mem_size16384`
`SRAM_MEM_0_FILE"NONE"`	`SRAM_MEM_0_FILE"NONE"`
`SRAM_MEM_1_FILE"NONE"`	`SRAM_MEM_1_FILE"NONE"`
`SRAM_MEM_2_FILE"NONE"`	`SRAM_MEM_2_FILE"NONE"`
`SRAM_MEM_3_FILE"NONE"`	`SRAM_MEM_3_FILE"NONE"`
Line 368...	Line 288...









	`fs-common`




	`../verilog/top.body`
	`verilogSourcefragment`







	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/common/wb_memory_def`
	`verilogSourcemodule`




	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`













	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/common/wb_memory_def`
	`verilogSourcemodule`




	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`

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