URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_big.xml] - Diff between revs 133 and 134

Rev 133	Rev 134
Line 164...	Line 164...






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`








`gen_registers`	`gen_registers`
Line 211...	Line 197...
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.bus16_big`	`wb_uart16550_bus16_big`


`dest_dir`
`../verilog`





Line 257...	Line 239...





`../verilog/common/top.bus16_big`	`../verilog/common/wb_uart16550_bus16_big`
`verilogSourcemodule`	`verilogSourcemodule`




Line 345...	Line 327...





`../verilog/common/top.bus16_big`	`../verilog/common/wb_uart16550_bus16_big`
`verilogSourcemodule`	`verilogSourcemodule`




Line 489...	Line 471...






`wb_addr_width8`
`wb_data_width16`
`wb_byte_lanes2`
`PRESCALER_PRESET16'h1234`





`baud_o`	`baud_o`
`wire`	`wire`
`out`	`out`