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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_lit.xml] - Diff between revs 133 and 134

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Rev 133 Rev 134
Line 165... Line 165...
 
 
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
  102.1
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_registers
  gen_registers
Line 212... Line 198...
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
   
   
    
    
      destination
      destination
      top.bus16_lit
      wb_uart16550_bus16_lit
    
 
    
 
      dest_dir
 
      ../verilog
 
    
    
  
  
 
 
 
 
 
 
Line 257... Line 239...
        verilogSourceinclude
        verilogSourceinclude
      
      
 
 
      
      
        
        
        ../verilog/common/top.bus16_lit
        ../verilog/common/wb_uart16550_bus16_lit
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
      
      
Line 339... Line 321...
        verilogSourceinclude
        verilogSourceinclude
      
      
 
 
      
      
        
        
        ../verilog/common/top.bus16_lit
        ../verilog/common/wb_uart16550_bus16_lit
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
 
 
Line 487... Line 469...
      
      
 
 
 
 
 
 
 
 
 
 
wb_addr_width8
 
wb_data_width16
 
wb_byte_lanes2
 
PRESCALER_PRESET16'h1234
 
 
 
 
 
 
 
 
 
 
 
baud_o
baud_o
  wire
  wire
  out
  out

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