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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 82...	Line 82...


`adr`	`adr`

`wb_adr_i`	`wb_adr_i`
`wb_addr_width-10`	`WB_ADDR_WIDTH-10`





`wdata`	`wdata`

`wb_dat_i`	`wb_dat_i`
`wb_data_width-10`	`WB_DATA_WIDTH-10`





`rdata`	`rdata`

`wb_dat_o`	`wb_dat_o`
`wb_data_width-10`	`WB_DATA_WIDTH-10`





Line 164...	Line 164...






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`








`gen_registers`	`gen_registers`
`102.1`	`102.1`
Line 210...	Line 195...
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top`	`wb_uart16550_def`


`dest_dir`
`../verilog`





Line 239...	Line 220...
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top`	`../verilog/common/wb_uart16550_def`
`verilogSourcemodule`	`verilogSourcemodule`




Line 322...	Line 303...
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top`	`../verilog/common/wb_uart16550_def`
`verilogSourcemodule`	`verilogSourcemodule`




Line 483...	Line 464...







`wb_addr_width8`
`wb_data_width8`
`wb_byte_lanes1`
`PRESCALER_PRESET16'h1234`










`baud_o`	`baud_o`

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