OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_big_tb.xml] - Diff between revs 133 and 134

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 133 Rev 134
Line 58... Line 58...
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
    
    
    
    
      destination
      destination
      top.bus16_big_tb
      wb_uart16550_bus16_big_tb
    
 
    
 
      dest_dir
 
      ../verilog
 
    
 
    
 
      top
 
    
    
  
  
 
 
 
 
 
 
Line 197... Line 190...
 
 
 
 
 
 
      
      
        
        
        ../verilog/common/top.bus16_big_tb
        ../verilog/common/wb_uart16550_bus16_big_tb
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
 
 
Line 216... Line 209...
 
 
 
 
 
 
      
      
        
        
        ../verilog/common/top.bus16_big_tb
        ../verilog/common/wb_uart16550_bus16_big_tb
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.