URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_big_tb.xml] - Diff between revs 133 and 134

Rev 133	Rev 134
Line 57...	Line 57...
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.bus32_big_tb`	`wb_uart16550_bus32_big_tb`


`dest_dir`
`../verilog`


`top`





Line 195...	Line 188...

`fs-sim`	`fs-sim`



`../verilog/common/top.bus32_big_tb`	`../verilog/common/wb_uart16550_bus32_big_tb`
`verilogSourcemodule`	`verilogSourcemodule`




Line 207...	Line 200...

`fs-lint`	`fs-lint`



`../verilog/common/top.bus32_big_tb`	`../verilog/common/wb_uart16550_bus32_big_tb`
`verilogSourcemodule`	`verilogSourcemodule`