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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_lint.xml] - Diff between revs 131 and 133

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Rev 131 Rev 133
Line 37... Line 37... 
opencores.org
 
opencores.org
 
wishbone
 
wishbone
 
wb_uart16550
 
wb_uart16550
 
bus32_lit_lint
 
bus32_lit_lint
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
 
 
  102.1
 
 
 
  none
 
 
 
  :*Simulation:*
 
 
 
>
 
 
 
  ./tools/verilog/elab_verilog
 
 
 
    
 
 
    
 
 
      configuration
 
 
 
      default
 
 
 
    
 
 
    
 
 
      dest_dir
 
 
 
      io_ports
 
 
 
    
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_design
 
 
 
  102.1
 
 
 
  none
 
 
 
  :*Simulation:*
 
 
 
>
 
 
 
  ./tools/verilog/gen_design
 
 
 
    
 
 
    
 
 
      dest_dir
 
 
 
      io_ports
 
 
 
    
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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