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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_def_tb.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
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`elab_verilog`
`103.0`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`



`trace_bus`
`103.0`
`none`
`:Simulation:`
`./tools/verilog/trace_bus`


`path`
`root.dut`


`bus_name`
`wb`








`gen_header`
`102.0`
`none`
`headers`
`./tools/regtool/gen_header`


`inst_path`
`dut.wb`


`dest_dir`
`../../../sw/`








`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`

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