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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [xml/] [clock_gen_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 50...	Line 50...



`clk`	`clk`
`clk`	`clk`
`reg`	`wire`





Line 85...	Line 85...





`elab_verilog`	`gen_verilog_sim`
`103.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/elab_verilog`	`./tools/verilog/gen_verilog`


`dest_dir`	`destination`
`io_ports`	`clock_gen_def`








`gen_design`	`gen_verilog_syn`
`103.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Synthesis:`
`./tools/verilog/gen_design`	`./tools/verilog/gen_verilog`


`dest_dir`	`destination`
`io_ports`	`clock_gen_def`
























`fs-sim`


`dest_dir`
`../verilog/sim/`
`verilogSourcelibraryDir`






`fs-syn`


`dest_dir`
`../verilog/syn/`
`verilogSourcelibraryDir`








	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`








`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`

Line 243...	Line 226...








	`fs-common`








	`fs-sim`



	`../verilog/clock_gen_sim`
	`verilogSourcefragment`





	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/sim/clock_gen_def`
	`verilogSourcemodule`




	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`






	`fs-syn`



	`../verilog/clock_gen_syn`
	`verilogSourcefragment`





	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/syn/clock_gen_def`
	`verilogSourcemodule`




	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`

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