URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [display_model/] [rtl/] [xml/] [display_model_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 37...	Line 37...
`opencores.org`	`opencores.org`
`Testbench`	`Testbench`
`display_model`	`display_model`
`def default`	`def default`










`gen_verilog_sim`
`104.0`
`none`
`:Simulation:`
`./tools/verilog/gen_verilog`


`destination`
`top.out.sim`


`dest_dir`
`../verilog`






`gen_verilog_syn`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`:Synthesis:`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.syn`	`display_model_def`


`dest_dir`
`../verilog`







`gen_verilogLib_sim`
`105.0`
`none`
`:Simulation:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`sim`





`gen_verilogLib_syn`
`105.0`
`none`
`:Synthesis:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`syn`











`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/sim/top.out.sim`
`verilogSourcemodule`





`../verilog/top.rtl`
`verilogSourcefragment`





`dest_dir../views/sim/`
`verilogSourcelibraryDir`
















`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/syn/top.out.syn`
`verilogSourcemodule`





`../verilog/top.rtl`
`verilogSourcefragment`







`dest_dir../views/syn/`
`verilogSourcelibraryDir`








	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`






	`commoncommon`
	`Verilog`


	`fs-common`










`sim:Simulation:`	`sim:Simulation:`

`Verilog`	`Verilog`
Line 307...	Line 180...








	`fs-common`



	`../verilog/top.rtl`
	`verilogSourcefragment`










	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/common/display_model_def`
	`verilogSourcemodule`




	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`













	`fs-syn`




	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/common/display_model_def`
	`verilogSourcemodule`



	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [display_model/] [rtl/] [xml/] [display_model_def.xml] - Diff between revs 133 and 134