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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_def.xml] - Diff between revs 133 and 134

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Rev 133 Rev 134
Line 46... Line 46...
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
  103.0
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog_sim
  gen_verilog_sim
  104.0
  104.0
  none
  none
  :*Simulation:*
  :*Simulation:*
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
    
    
    
    
      destination
      destination
      top.out.sim
      io_probe_def
    
 
    
 
      dest_dir
 
      ../verilog
 
    
    
  
  
 
 
 
 
 
 
Line 91... Line 69...
  :*Synthesis:*
  :*Synthesis:*
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
    
    
    
    
      destination
      destination
      top.out.syn
      io_probe_def
    
 
    
 
      dest_dir
 
      ../verilog
 
    
    
  
  
 
 
 
 
 
 
 
 
 
 
  gen_verilogLib_sim
 
  105.0
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/gen_verilogLib
 
    
 
    
 
      dest_dir
 
      ../views
 
    
 
    
 
      view
 
      sim
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
  gen_verilogLib_syn
 
  105.0
 
  none
 
  :*Synthesis:*
 
  ./tools/verilog/gen_verilogLib
 
    
 
    
 
      dest_dir
 
      ../views
 
    
 
    
 
      view
 
      syn
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
    
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright.v
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/sim/top.out.sim
 
        verilogSourcemodule
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/top.body
 
        verilogSourcefragment
 
      
 
 
 
      
 
        dest_dir../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
 
 
 
 
    
 
 
       
 
 
    
 
      fs-syn
 
 
 
      
 
        
 
        ../verilog/copyright.v
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/syn/top.out.syn
 
        verilogSourcemodule
 
      
 
 
 
      
 
        dest_dir../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
            
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
 
 
 
       
 
 
 
 
 
 
 
              
              
              sim:*Simulation:*
              sim:*Simulation:*
Line 313... Line 194...
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
    
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/sim/io_probe_def
 
        verilogSourcemodule
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/top.body
 
        verilogSourcefragment
 
      
 
 
 
      
 
        dest_dir../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
 
 
 
 
    
 
 
 
 
 
    
 
      fs-syn
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/syn/io_probe_def
 
        verilogSourcemodule
 
      
 
 
 
      
 
        dest_dir../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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