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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 1...	Line 1...


`// //`	`// //`
`// Author : John Eaton Ouabache Designworks //`	`// Author : John Eaton Ouabache Designworks //`
`// //`	`// //`
`// Copyright (C) 2010 Authors and OPENCORES.ORG //`	`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
Line 37...	Line 37...
`opencores.org`	`opencores.org`
`Testbench`	`Testbench`
`io_probe`	`io_probe`
`in default`	`in default`












`elab_verilog`
`103.0`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`









`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.in.sim`	`io_probe_in`


`dest_dir`
`../verilog`





Line 92...	Line 62...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.in.syn`	`io_probe_in`


`dest_dir`
`../verilog`





Line 143...	Line 109...








`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/sim/top.in.sim`
`verilogSourcemodule`





`../verilog/top.body.in`
`verilogSourcefragment`



`dest_dir../views/sim/`
`verilogSourcelibraryDir`










`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/syn/top.in.syn`
`verilogSourcemodule`



`dest_dir../views/syn/`
`verilogSourcelibraryDir`




















	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`











`sim:Simulation:`	`sim:Simulation:`
Line 305...	Line 215...








	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/sim/io_probe_in`
	`verilogSourcemodule`





	`../verilog/top.body.in`
	`verilogSourcefragment`



	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`










	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/syn/io_probe_in`
	`verilogSourcemodule`



	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Diff between revs 133 and 134