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/**********************************************************************/

/*                                                                    */

/*             -------                                                */

/*            /   SOC  \                                              */

/*           /    GEN   \                                             */

/*          /     SIM    \                                            */

/*          ==============                                            */

/*          |            |                                            */

/*          |____________|                                            */

/*                                                                    */

/*  Microprocessor bus functional model (BFM) for simulations         */

/*                                                                    */

/*                                                                    */

/*  Author(s):                                                        */

/*      - John Eaton, jt_eaton@opencores.org                          */

/*                                                                    */

/**********************************************************************/

/*                                                                    */

/*    Copyright (C) <2010>                     */

/*                                                                    */

/*  This source file may be used and distributed without              */

/*  restriction provided that this copyright statement is not         */

/*  removed from the file and that any derivative work contains       */

/*  the original copyright notice and the associated disclaimer.      */

/*                                                                    */

/*  This source file is free software; you can redistribute it        */

/*  and/or modify it under the terms of the GNU Lesser General        */

/*  Public License as published by the Free Software Foundation;      */

/*  either version 2.1 of the License, or (at your option) any        */

/*  later version.                                                    */

/*                                                                    */

/*  This source is distributed in the hope that it will be            */

/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */

/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */

/*  PURPOSE.  See the GNU Lesser General Public License for more      */

/*  details.                                                          */

/*                                                                    */

/*  You should have received a copy of the GNU Lesser General         */

/*  Public License along with this source; if not, download it        */

/*  from http://www.opencores.org/lgpl.shtml                          */

/*                                                                    */

/**********************************************************************/

module micro_bus16_model_def

module micro_bus16_model_def

#(parameter OUT_DELAY    = 15,

#(parameter DELAY    = 15,

  parameter OUT_WIDTH    = 10

  parameter WIDTH    = 16

  input wire                  clk,

  input wire                  clk,

  input wire                  reset,

  input wire                  reset,

  input  wire [15:0]          rdata,

  output reg [23:0]           addr,

  output reg [23:0]           addr,

  output reg [15:0]           wdata,

  output reg [15:0]           wdata,

  output reg [1:0]            cs,

  output reg [1:0]            cs,

  output reg                  rd,

  output reg                  rd,

  output reg                  wr,

  output reg                  wr,

  output reg                  ub,

  output reg                  ub,

  output reg                  lb,

  output reg                  lb

  inout  wire [15:0]           rdata

);

);

   reg [15:0]  exp_rdata;

   reg [15:0]  exp_rdata;

   reg [15:0]  mask_rdata;

   reg [15:0]  mask_rdata;

io_probe_in

 #(.MESG         ("micro rdata Error"),

   .WIDTH        (WIDTH),

   .IN_DELAY     (DELAY)

rdata_tpb

  .clk            (  clk        ),

  .expected_value (  exp_rdata  ),

  .mask           (  mask_rdata ),

  .signal         (  rdata      )

);

always@(posedge clk)

always@(posedge clk)

  if(reset)

  if(reset)

    begin

    begin

      addr  <= 24'h0000;

      addr  <= 24'h0000;

      wdata <=  16'h0000;

      wdata <=  16'h0000;

Line 86...

Line 64...

      mask_rdata    <=  16'h0000;

      mask_rdata    <=  16'h0000;

end

end

io_probe_def

 #(.MESG         ("micro rdata Error"),

   .WIDTH        (16),

   .RESET        ({16{1'bz}}),

   .OUT_DELAY    (OUT_DELAY),

   .OUT_WIDTH    (OUT_WIDTH)

rdata_tpb

  .clk            (  clk        ),

  .drive_value    (16'bzzzzzzzzzzzzzzzz  ),

  .expected_value (  exp_rdata  ),

  .mask           (  mask_rdata ),

  .signal         (  rdata      )

);

  // Tasks

  // Tasks

Rev 131	Rev 134
Line 1...	Line 1...
`/**********************************************************************/`
`/* */`
`/* ------- */`
`/* / SOC \ */`
`/* / GEN \ */`
`/* / SIM \ */`
`/* ============== */`
`/* \| \| */`
`/* \|____________\| */`
`/* */`
`/* Microprocessor bus functional model (BFM) for simulations */`
`/* */`
`/* */`
`/* Author(s): */`
`/* - John Eaton, jt_eaton@opencores.org */`
`/* */`
`/**********************************************************************/`
`/* */`
`/* Copyright (C) <2010> */`
`/* */`
`/* This source file may be used and distributed without */`
`/* restriction provided that this copyright statement is not */`
`/* removed from the file and that any derivative work contains */`
`/* the original copyright notice and the associated disclaimer. */`
`/* */`
`/* This source file is free software; you can redistribute it */`
`/* and/or modify it under the terms of the GNU Lesser General */`
`/* Public License as published by the Free Software Foundation; */`
`/* either version 2.1 of the License, or (at your option) any */`
`/* later version. */`
`/* */`
`/* This source is distributed in the hope that it will be */`
`/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
`/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
`/* PURPOSE. See the GNU Lesser General Public License for more */`
`/* details. */`
`/* */`
`/* You should have received a copy of the GNU Lesser General */`
`/* Public License along with this source; if not, download it */`
`/* from http://www.opencores.org/lgpl.shtml */`
`/* */`
`/**********************************************************************/`






`module micro_bus16_model_def`	`module micro_bus16_model_def`
`#(parameter OUT_DELAY = 15,`	`#(parameter DELAY = 15,`
`parameter OUT_WIDTH = 10`	`parameter WIDTH = 16`
`)`	`)`


`(`	`(`
`input wire clk,`	`input wire clk,`
`input wire reset,`	`input wire reset,`
	`input wire [15:0] rdata,`

`output reg [23:0] addr,`	`output reg [23:0] addr,`
`output reg [15:0] wdata,`	`output reg [15:0] wdata,`
`output reg [1:0] cs,`	`output reg [1:0] cs,`
`output reg rd,`	`output reg rd,`
`output reg wr,`	`output reg wr,`
`output reg ub,`	`output reg ub,`
`output reg lb,`	`output reg lb`


`inout wire [15:0] rdata`
`);`	`);`


`reg [15:0] exp_rdata;`	`reg [15:0] exp_rdata;`
`reg [15:0] mask_rdata;`	`reg [15:0] mask_rdata;`



	`io_probe_in`
	`#(.MESG ("micro rdata Error"),`
	`.WIDTH (WIDTH),`
	`.IN_DELAY (DELAY)`
	`)`
	`rdata_tpb`
	`(`
	`.clk ( clk ),`
	`.expected_value ( exp_rdata ),`
	`.mask ( mask_rdata ),`
	`.signal ( rdata )`
	`);`













`always@(posedge clk)`	`always@(posedge clk)`
`if(reset)`	`if(reset)`
`begin`	`begin`
`addr <= 24'h0000;`	`addr <= 24'h0000;`
`wdata <= 16'h0000;`	`wdata <= 16'h0000;`
Line 86...	Line 64...
`mask_rdata <= 16'h0000;`	`mask_rdata <= 16'h0000;`
`end`	`end`



`io_probe_def`
`#(.MESG ("micro rdata Error"),`
`.WIDTH (16),`
`.RESET ({16{1'bz}}),`
`.OUT_DELAY (OUT_DELAY),`
`.OUT_WIDTH (OUT_WIDTH)`
`)`
`rdata_tpb`
`(`
`.clk ( clk ),`
`.drive_value (16'bzzzzzzzzzzzzzzzz ),`
`.expected_value ( exp_rdata ),`
`.mask ( mask_rdata ),`
`.signal ( rdata )`
`);`


`// Tasks`	`// Tasks`

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