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/**********************************************************************/
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/* */
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/* ------- */
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/* / SOC \ */
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/* / GEN \ */
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/* / SIM \ */
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/* ============== */
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/* | | */
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/* |____________| */
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/* */
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/* Microprocessor bus functional model (BFM) for simulations */
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/* */
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/* */
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/* Author(s): */
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/* - John Eaton, jt_eaton@opencores.org */
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/* */
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/**********************************************************************/
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/* */
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/* Copyright (C) <2010> <Ouabache Design Works> */
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/* */
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/* This source file may be used and distributed without */
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/* restriction provided that this copyright statement is not */
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/* removed from the file and that any derivative work contains */
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/* the original copyright notice and the associated disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it */
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/* and/or modify it under the terms of the GNU Lesser General */
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/* Public License as published by the Free Software Foundation; */
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/* either version 2.1 of the License, or (at your option) any */
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/* later version. */
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/* */
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/* This source is distributed in the hope that it will be */
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/* useful, but WITHOUT ANY WARRANTY; without even the implied */
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/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
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/* PURPOSE. See the GNU Lesser General Public License for more */
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/* details. */
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/* */
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/* You should have received a copy of the GNU Lesser General */
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/* Public License along with this source; if not, download it */
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/* from http://www.opencores.org/lgpl.shtml */
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/* */
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/**********************************************************************/
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module micro_bus16_model_def
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module micro_bus16_model_def
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#(parameter OUT_DELAY = 15,
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#(parameter DELAY = 15,
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parameter OUT_WIDTH = 10
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parameter WIDTH = 10
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)
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)
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(
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(
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input wire clk,
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input wire clk,
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input wire reset,
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input wire reset,
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input wire [15:0] rdata,
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output reg [23:0] addr,
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output reg [23:0] addr,
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output reg [15:0] wdata,
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output reg [15:0] wdata,
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output reg [1:0] cs,
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output reg [1:0] cs,
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output reg rd,
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output reg rd,
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output reg wr,
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output reg wr,
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output reg ub,
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output reg ub,
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output reg lb,
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output reg lb
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inout wire [15:0] rdata
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);
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);
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reg [15:0] exp_rdata;
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reg [15:0] exp_rdata;
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reg [15:0] mask_rdata;
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reg [15:0] mask_rdata;
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always@(posedge clk)
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if(reset)
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begin
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addr <= 24'h0000;
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wdata <= 16'h0000;
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wr <= 1'b0;
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rd <= 1'b0;
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cs <= 2'b00;
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ub <= 1'b0;
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lb <= 1'b0;
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exp_rdata <= 16'h0000;
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mask_rdata <= 16'h0000;
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end
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io_probe_def
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io_probe_in
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#(.MESG ("micro rdata Error"),
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#(.MESG ("micro rdata Error"),
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.WIDTH (16),
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.WIDTH (16)
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.RESET ({16{1'bz}}),
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.OUT_DELAY (OUT_DELAY),
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.OUT_WIDTH (OUT_WIDTH)
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)
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)
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rdata_tpb
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rdata_tpb
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(
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(
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.clk ( clk ),
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.clk ( clk ),
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.drive_value (16'bzzzzzzzzzzzzzzzz ),
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.expected_value ( exp_rdata ),
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.expected_value ( exp_rdata ),
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.mask ( mask_rdata ),
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.mask ( mask_rdata ),
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.signal ( rdata )
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.signal ( rdata )
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);
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);
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always@(posedge clk)
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if(reset)
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begin
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addr <= 24'h000000;
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wdata <= 16'h0000;
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wr <= 1'b0;
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rd <= 1'b0;
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cs <= 2'b00;
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ub <= 1'b0;
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lb <= 1'b0;
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exp_rdata <= 16'h0000;
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mask_rdata <= 16'h0000;
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end
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