URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [xml/] [micro_bus16_model_def.xml] - Diff between revs 131 and 134

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Rev 131	Rev 134
Line 46...	Line 46...





`gen_verilogLib_sim`	`gen_verilog_sim`
`105.0`	`105.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilogLib`	`./tools/verilog/gen_verilog`


`dest_dir`	`destination`
`../views`	`micro_bus16_model_def`


`view`
`sim`






`gen_verilogLib_syn`	`gen_verilog_syn`
`105.0`	`105.0`
`none`	`none`
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilogLib`	`./tools/verilog/gen_verilog`


`dest_dir`	`destination`
`../views`	`micro_bus16_model_def`


`view`
`syn`











`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`





`../verilog/top.sim`
`verilogSourcemodule`



`dest_dir../views/sim/`
`verilogSourcelibraryDir`








`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`





`../verilog/top.syn`
`verilogSourcemodule`



`dest_dir../views/syn/`
`verilogSourcelibraryDir`













`Hierarchical`	`Hierarchical`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="io_probe"`	`spirit:name="micro_bus16_model"`
`spirit:version="def.design"/>`	`spirit:version="def.design"/>`





	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`







`sim:Simulation:`	`sim:Simulation:`

`Verilog`	`Verilog`


Line 197...	Line 148...





`OUT_DELAY15`	`DELAY15`
`OUT_WIDTH10`	`WIDTH16`




`clk`	`clk`
Line 248...	Line 199...
`out`	`out`


`rdata`	`rdata`
`wire`	`wire`
`inout`	`in`
`150`	`150`



	`cs`
	`reg`
	`out`
	`10`













	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`





	`../verilog/logic`
	`verilogSourcefragment`





	`../verilog/tasks`
	`verilogSourcefragment`




	`../verilog/sim/micro_bus16_model_def`
	`verilogSourcemodule`




	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`








	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`





	`../verilog/logic`
	`verilogSourcefragment`





	`../verilog/syn/micro_bus16_model_def`
	`verilogSourcemodule`



	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [xml/] [micro_bus16_model_def.xml] - Diff between revs 131 and 134