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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [verilog/] [top.syn] - Diff between revs 131 and 133

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Rev 131 Rev 133
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module micro_bus_model_def
 
 
 
#(parameter addr_width   = 16,
 
 
 
  parameter OUT_DELAY    = 15,
 
 
 
  parameter OUT_WIDTH    = 10
 
 
 
  )
 
 
 
 
 
 
 
 
 
 
 
 (
 
 
 
  input wire                  clk,
 
 
 
  input wire                  reset,
 
 
 
 
 
 
 
  output reg [addr_width-1:0]           addr,
 
 
 
  output reg [7:0]            wdata,
 
 
 
  output reg                  rd,
 
 
 
  output reg                  wr,
 
 
 
  output reg                  cs,
 
 
 
 
 
 
 
  input  wire [7:0]           rdata
 
 
 
);
 
 
 
 
 
 
 
 
 
 
 
   reg [7:0]  exp_rdata;
 
 
 
   reg [7:0]  mask_rdata;
 
 
 
 
 
 
 
always@(posedge clk)
 
always@(posedge clk)
 
  if(reset)
 
  if(reset)
 
    begin
 
    begin
 
      addr          <= 16'h0000;
 
      addr          <= 16'h0000;
 
      wdata         <=  8'h00;
 
      wdata         <=  8'h00;
Line 35... Line 11... 
      mask_rdata    <=  8'h00;
 
      mask_rdata    <=  8'h00;
 
   end
 
   end
 
 
 
 
 
 
 
 
 
 
 
 
 
io_probe_in
 
 
 
 #(.MESG         ("micro rdata Error"),
 
 
 
   .WIDTH        (8)
 
 
 
  )
 
 
 
rdata_tpb
 
 
 
  (
 
 
 
  .clk            (  clk        ),
 
 
 
  .expected_value (  exp_rdata  ),
 
 
 
  .mask           (  mask_rdata ),
 
 
 
  .signal         (  rdata      )
 
 
 
  );
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
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