URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [xml/] [micro_bus_model_def.xml] - Diff between revs 133 and 134

Rev 133	Rev 134
Line 97...	Line 97...












`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`








`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top`	`micro_bus_model_def`


`dest_dir`
`../verilog`





Line 150...	Line 125...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top`	`micro_bus_model_def`


`dest_dir`
`../verilog`










`gen_verilogLib_sim`
`105.0`
`none`
`:Simulation:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`sim`





`gen_verilogLib_syn`
`105.0`
`none`
`:Synthesis:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`syn`





Line 224...	Line 154...
`verilogSourcefragment`	`verilogSourcefragment`




`../verilog/sim/top`	`../verilog/sim/micro_bus_model_def`
`verilogSourcemodule`	`verilogSourcemodule`



`dest_dir../views/sim/`	`dest_dir../views/sim/`
Line 257...	Line 187...
`verilogSourcefragment`	`verilogSourcefragment`




`../verilog/syn/top`	`../verilog/syn/micro_bus_model_def`
`verilogSourcemodule`	`verilogSourcemodule`




Line 291...	Line 221...
`spirit:name="micro_bus_model"`	`spirit:name="micro_bus_model"`
`spirit:version="def.design"/>`	`spirit:version="def.design"/>`



	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`











`sim:Simulation:`	`sim:Simulation:`

`Verilog`	`Verilog`