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/**********************************************************************/
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/* */
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/* ------- */
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/* / SOC \ */
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/* / GEN \ */
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/* / SIM \ */
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/* ============== */
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/* | | */
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/* |____________| */
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/* */
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/* ps2 host model for simulations */
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/* */
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/* */
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/* Author(s): */
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/* - John Eaton, jt_eaton@opencores.org */
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/* */
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/**********************************************************************/
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/* */
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/* Copyright (C) <2010> <Ouabache Design Works> */
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/* */
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/* This source file may be used and distributed without */
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/* restriction provided that this copyright statement is not */
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/* removed from the file and that any derivative work contains */
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/* the original copyright notice and the associated disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it */
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/* and/or modify it under the terms of the GNU Lesser General */
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/* Public License as published by the Free Software Foundation; */
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/* either version 2.1 of the License, or (at your option) any */
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/* later version. */
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/* */
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/* This source is distributed in the hope that it will be */
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/* useful, but WITHOUT ANY WARRANTY; without even the implied */
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/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
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/* PURPOSE. See the GNU Lesser General Public License for more */
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/* details. */
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/* */
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/* You should have received a copy of the GNU Lesser General */
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/* Public License along with this source; if not, download it */
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/* from http://www.opencores.org/lgpl.shtml */
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/* */
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/**********************************************************************/
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module ps2_host_def
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module ps2_host_def
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(
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(
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input wire clk,
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input wire clk,
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input wire reset,
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input wire reset,
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input wire busy,
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input wire busy,
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inout wire [7:0] rx_data,
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input wire [7:0] rx_data,
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input wire rx_read,
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input wire rx_read,
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input wire rx_full,
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input wire rx_full,
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input wire rx_parity_error,
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input wire rx_parity_error,
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input wire rx_parity_rcv,
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input wire rx_parity_rcv,
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input wire rx_parity_cal,
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input wire rx_parity_cal,
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reg [7:0] exp_rcv_byte;
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reg [7:0] exp_rcv_byte;
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reg [7:0] mask_rcv_byte;
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reg [7:0] mask_rcv_byte;
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always@(posedge clk)
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always@(posedge clk)
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if(reset)
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if(reset)
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begin
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begin
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tx_data <= 8'h00;
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tx_data <= 8'h00;
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tx_write <= 1'b0;
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tx_write <= 1'b0;
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