URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [xml/] [ps2_host_def.xml] - Diff between revs 131 and 134

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Rev 131	Rev 134
Line 39...	Line 39...
`ps2_host`	`ps2_host`
`def default`	`def default`







`gen_verilogLib_sim`	`gen_verilog_sim`
`105.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilogLib`	`./tools/verilog/gen_verilog`


`dest_dir`	`destination`
`../views`	`ps2_host_def`


`view`
`sim`







`gen_verilogLib_syn`	`gen_verilog_syn`
`105.0`	`104.0`
`none`	`none`
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilogLib`	`./tools/verilog/gen_verilog`


`dest_dir`	`destination`
`../views`	`ps2_host_def`


`view`
`syn`











`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/top.sim`
`verilogSourcemodule`




`dest_dir../views/sim/`
`verilogSourcelibraryDir`






`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/top.syn`
`verilogSourcemodule`



`dest_dir../views/syn/`
`verilogSourcelibraryDir`




















`Hierarchical`	`Hierarchical`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="io_probe"`	`spirit:name="ps2_host"`
`spirit:version="def.design"/>`	`spirit:version="def.design"/>`




`sim:Simulation:`	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`









	`sim:Simulation:`
`Verilog`	`Verilog`


`fs-sim`	`fs-sim`




`syn:Synthesis:`	`syn:Synthesis:`

`Verilog`	`Verilog`


`fs-syn`	`fs-syn`

Line 229...	Line 187...
`rx_parity_cal`	`rx_parity_cal`
`wire`	`wire`
`in`	`in`


	`tx_ack_error`
	`wire`
	`in`


`rx_frame_error`	`rx_frame_error`
`wire`	`wire`
`in`	`in`


`rx_clr`	`rx_clr`
`wire`	`reg`
`out`	`out`




`tx_write`	`tx_write`
`wire`	`reg`
`out`	`out`




	`tx_data`
	`reg`
	`out70`




	`rx_data`
	`wire`
	`in70`











	`fs-sim`



	`../verilog/logic`
	`verilogSourcefragment`




	`../verilog/tasks`
	`verilogSourcefragment`





	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/sim/ps2_host_def`
	`verilogSourcemodule`




	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`






	`fs-syn`



	`../verilog/logic`
	`verilogSourcefragment`




	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/syn/ps2_host_def`
	`verilogSourcemodule`



	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [xml/] [ps2_host_def.xml] - Diff between revs 131 and 134