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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [xml/] [ps2_model_def.xml] - Diff between revs 134 and 135

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Rev 134 Rev 135
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//   You should have received a copy of the GNU Lesser General            //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
//                                                                        //
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
Testbench
Testbench
ps2_model
ps2_model
def  default
def
 
 
 
 
 
 
 
 
  gen_verilog_sim
  gen_verilog_sim
  104.0
  104.0
  none
  none
  :*Simulation:*
  :*Simulation:*
  ./tools/verilog/gen_verilog
  tools/verilog/gen_verilog
    
    
    
    
      destination
      destination
      ps2_model_def
      ps2_model_def
    
    
  
  
 
 
 
 
 
 
 
 
  gen_verilog_syn
  gen_verilog_syn
  104.0
  104.0
  none
  none
  :*Synthesis:*
  :*Synthesis:*
  ./tools/verilog/gen_verilog
  tools/verilog/gen_verilog
    
    
    
    
      destination
      destination
      ps2_model_def
      ps2_model_def
    
    
  
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
  
 
 
    
    
      fs-sim
      fs-sim
 
 
      
      
        
        
        ../verilog/copyright
        ../verilog/copyright
        verilogSourceinclude
        verilogSourceinclude
      
      
 
 
      
      
        
        
        ../verilog/sim/ps2_model_def
        ../verilog/sim/ps2_model_def
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
      
      
        
        
        ../verilog/top.rtl
        ../verilog/top.rtl
        verilogSourcefragment
        verilogSourcefragment
      
      
 
 
      
      
        
        
        ../verilog/top.tasks
        ../verilog/top.tasks
        verilogSourcefragment
        verilogSourcefragment
      
      
 
 
      
      
        dest_dir../views/sim/
        dest_dir../views/sim/
        verilogSourcelibraryDir
        verilogSourcelibraryDir
      
      
 
 
 
 
 
 
 
 
 
 
    
    
 
 
 
 
 
 
 
 
    
    
      fs-syn
      fs-syn
 
 
      
      
        
        
        ../verilog/copyright
        ../verilog/copyright
        verilogSourceinclude
        verilogSourceinclude
      
      
 
 
 
 
      
      
        
        
        ../verilog/syn/ps2_model_def
        ../verilog/syn/ps2_model_def
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
      
      
        
        
        ../verilog/top.rtl
        ../verilog/top.rtl
        verilogSourcefragment
        verilogSourcefragment
      
      
 
 
      
      
        dest_dir../views/syn/
        dest_dir../views/syn/
        verilogSourcelibraryDir
        verilogSourcelibraryDir
      
      
 
 
 
 
    
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
  
 
 
 
 
 
 
 
 
       
 
 
 
              
 
              Hierarchical
 
 
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="ps2_model"
 
                                   spirit:version="def.design"/>
 
              
 
 
 
 
        
 
                        
 
                                Hierarchical
 
                                
 
                        
 
                
 
 
 
 
 
 
             
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
 
  
 
 
 
              
 
              Hierarchical
 
                     Hierarchical
 
              
 
 
 
 
 
 
 
 
              
             
              sim:*Simulation:*
              verilog
 
              
 
              
 
                                   ipxact:library="Testbench"
 
                                   ipxact:name="toolflow"
 
                                   ipxact:version="verilog"/>
 
              
 
              
 
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
              
 
              syn:*Synthesis:*
 
 
 
              Verilog
 
              
 
                     
 
                            fs-syn
 
                     
 
              
 
 
 
              
 
              doc
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
 
 
 
 
              
 
              sim:*Simulation:*
 
 
      
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
              
CLKCNT10'h1f0
              syn:*Synthesis:*
SIZE10
 
 
 
 
 
 
              Verilog
 
              
 
                     
 
                            fs-syn
 
                     
 
              
 
 
clk
              
wire
              doc
in
              
 
              
 
                                   ipxact:library="Testbench"
 
                                   ipxact:name="toolflow"
 
                                   ipxact:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
reset
 
wire
 
in
 
 
 
 
 
 
 
ps2_clk
      
wire
 
inout
 
 
 
 
 
ps2_data
 
wire
CLKCNT10'h1f0
inout
SIZE10
 
 
 
 
 
 
 
 
 
clk
 
wire
 
in
 
 
 
 
 
reset
 
wire
 
in
 
 
 
 
 
 
 
ps2_clk
 
wire
 
inout
 
 
 
 
 
ps2_data
 
wire
 
inout
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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