URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [xml/] [ps2_model_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 37...	Line 37...
`opencores.org`	`opencores.org`
`Testbench`	`Testbench`
`ps2_model`	`ps2_model`
`def default`	`def default`









`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`







`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.sim`	`ps2_model_def`


`dest_dir`
`../verilog`





Line 88...	Line 63...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.syn`	`ps2_model_def`


`dest_dir`
`../verilog`






`gen_verilogLib_sim`
`105.0`
`none`
`:Simulation:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`sim`






`gen_verilogLib_syn`
`105.0`
`none`
`:Synthesis:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`syn`









Line 147...	Line 81...

`fs-sim`	`fs-sim`



`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/sim/top.out.sim`	`../verilog/sim/ps2_model_def`
`verilogSourcemodule`	`verilogSourcemodule`




Line 189...	Line 123...

`fs-syn`	`fs-syn`



`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`





`../verilog/syn/top.out.syn`	`../verilog/syn/ps2_model_def`
`verilogSourcemodule`	`verilogSourcemodule`




Line 238...	Line 172...
`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="ps2_model"`	`spirit:name="ps2_model"`
`spirit:version="def.design"/>`	`spirit:version="def.design"/>`






	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`









`sim:Simulation:`	`sim:Simulation:`

`Verilog`	`Verilog`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [xml/] [ps2_model_def.xml] - Diff between revs 133 and 134