OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [top.sim] - Diff between revs 131 and 134

Show entire file | Details | Blame | View Log

Rev 131 Rev 134
Line 45... Line 45... 
 
 
 
 
 
 
 
 
module uart_host_def (
 
module uart_host_def (
 
input  wire           clk,
 
input  wire           clk,
 
input  wire           reset,
 
input  wire           reset,
 
 
 
input  wire           rxd_data_avail,
 
 
 
input  wire           rxd_stop_error,
 
 
 
input  wire           rxd_parity_error,
 
 
 
input  wire           txd_buffer_empty,
 
 
 
input  wire [7:0]     rxd_data_out,
 
output reg            parity_enable,
 
output reg            parity_enable,
 
output  reg           txd_parity,
 
output  reg           rxd_data_avail_stb,
 
 
 
output  reg           rxd_force_parity,
 
 
 
output  reg           rxd_parity,
 
 
 
output  reg           txd_break,
 
output  reg           txd_force_parity,
 
output  reg           txd_force_parity,
 
output  reg [7:0]     txd_data_in,
 
 
 
input  wire           txd_buffer_empty,
 
 
 
output  reg           txd_load,
 
output  reg           txd_load,
 
output  reg           txd_break,
 
output  reg           txd_parity,
 
output  reg           rxd_parity,
 
output  reg [7:0]     txd_data_in
 
output  reg           rxd_force_parity,
 
 
 
output  reg           rxd_data_avail_stb,
 
 
 
inout  wire [7:0]     rxd_data_out,
 
 
 
input  wire           rxd_data_avail,
 
 
 
inout  wire           rxd_stop_error,
 
 
 
inout  wire           rxd_parity_error
 
 
 
);
 
);
 
 
 
 
 
reg exp_rxd_stop_error;
 
reg exp_rxd_stop_error;
 
reg exp_rxd_parity_error;
 
reg exp_rxd_parity_error;
 
reg [7:0] exp_rxd_data_out;
 
reg [7:0] exp_rxd_data_out;
Line 72... Line 73... 
reg [7:0] mask_rxd_data_out;
 
reg [7:0] mask_rxd_data_out;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
io_probe_in
 
 
 
#(.MESG("uart_host receive error"),
 
 
 
  .WIDTH(8))
 
 
 
rxd_data_out_prb
 
 
 
(
 
 
 
       .clk            ( clk               ),
 
 
 
       .expected_value ( exp_rxd_data_out  ),
 
 
 
       .mask           ( mask_rxd_data_out ),
 
 
 
       .signal         ( rxd_data_out      )
 
 
 
);
 
 
 
 
 
task automatic next;
 
io_probe_in
 
  input [31:0] num;
 
#(.MESG("uart_host stop error"))
 
  repeat (num)       @ (posedge clk);
 
rxd_stop_error_prb
 
endtask
 
(
 
 
 
       .clk            ( clk                 ),
 
 
 
       .expected_value ( exp_rxd_stop_error  ),
 
 
 
       .mask           ( mask_rxd_stop_error ),
 
 
 
       .signal         ( rxd_stop_error      )
 
 
 
);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
io_probe_in
 
 
 
#(.MESG("uart_host parity error"))
 
 
 
rxd_parity_error_prb
 
 
 
(
 
 
 
       .clk            ( clk                   ),
 
 
 
       .expected_value ( exp_rxd_parity_error  ),
 
 
 
       .mask           ( mask_rxd_parity_error ),
 
 
 
       .signal         ( rxd_parity_error      )
 
 
 
 
 
 
 
 
 
 
 
);
 
 
 
 
 
 
 
 
 
always@(posedge clk)
 
always@(posedge clk)
 
if(reset)
 
if(reset)
 
  begin
 
  begin
 
  parity_enable        <= 1'b0;
 
  parity_enable        <= 1'b0;
 
  txd_data_in          <= 8'h00;
 
  txd_data_in          <= 8'h00;
Line 104... Line 134... 
 
 
 
 
 
 
 
 
 end
 
 end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
task automatic next;
 
 
 
  input [31:0] num;
 
 
 
  repeat (num)       @ (posedge clk);
 
 
 
endtask
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
task clear_rx_host;
 
task clear_rx_host;
 
 begin
 
 begin
 
 next(1);
 
 next(1);
 
 end
 
 end
 
endtask
 
endtask
Line 151... Line 192... 
   next(1);
 
   next(1);
 
end
 
end
 
endtask
 
endtask
 
 
 
 
 
 
 
 
 
io_probe_def
 
 
 
#(.MESG("uart_host receive error"),
 
 
 
  .WIDTH(8))
 
 
 
rxd_data_out_prb
 
 
 
(
 
 
 
       .clk            ( clk               ),
 
 
 
       .drive_value    (8'bzzzzzzzz        ),
 
 
 
       .expected_value ( exp_rxd_data_out  ),
 
 
 
       .mask           ( mask_rxd_data_out ),
 
 
 
       .signal         ( rxd_data_out      )
 
 
 
 
 
 
 
 
 
 
 
);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
io_probe_def
 
 
 
#(.MESG("uart_host stop error"))
 
 
 
rxd_stop_error_prb
 
 
 
(
 
 
 
       .clk            ( clk                 ),
 
 
 
       .drive_value    (1'bz                 ),
 
 
 
       .expected_value ( exp_rxd_stop_error  ),
 
 
 
       .mask           ( mask_rxd_stop_error ),
 
 
 
       .signal         ( rxd_stop_error      )
 
 
 
 
 
 
 
 
 
 
 
);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
io_probe_def
 
 
 
#(.MESG("uart_host parity error"))
 
 
 
rxd_parity_error_prb
 
 
 
(
 
 
 
       .clk            ( clk                 ),
 
 
 
       .drive_value    (1'bz                 ),
 
 
 
       .expected_value ( exp_rxd_parity_error  ),
 
 
 
       .mask           ( mask_rxd_parity_error ),
 
 
 
       .signal         ( rxd_parity_error      )
 
 
 
 
 
 
 
 
 
 
 
);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.