Line 55... |
Line 55... |
output reg txd_load,
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output reg txd_load,
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output reg txd_break,
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output reg txd_break,
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output reg rxd_parity,
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output reg rxd_parity,
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output reg rxd_force_parity,
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output reg rxd_force_parity,
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output reg rxd_data_avail_stb,
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output reg rxd_data_avail_stb,
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inout wire [7:0] rxd_data_out,
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input wire [7:0] rxd_data_out,
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input wire rxd_data_avail,
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input wire rxd_data_avail,
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inout wire rxd_stop_error,
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input wire rxd_stop_error,
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inout wire rxd_parity_error
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input wire rxd_parity_error
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);
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);
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reg exp_rxd_stop_error;
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reg exp_rxd_stop_error;
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reg exp_rxd_parity_error;
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reg exp_rxd_parity_error;
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reg [7:0] exp_rxd_data_out;
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reg [7:0] exp_rxd_data_out;
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Line 71... |
Line 71... |
reg mask_rxd_parity_error;
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reg mask_rxd_parity_error;
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reg [7:0] mask_rxd_data_out;
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reg [7:0] mask_rxd_data_out;
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io_probe_in
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always@(posedge clk)
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if(reset)
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begin
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parity_enable <= 1'b0;
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txd_data_in <= 8'h00;
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txd_parity <= 1'b0;
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txd_force_parity <= 1'b0;
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txd_load <= 1'b0;
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txd_break <= 1'b0;
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rxd_parity <= 1'b0;
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rxd_force_parity <= 1'b0;
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rxd_data_avail_stb <= 1'b0;
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exp_rxd_stop_error <= 1'b0;
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exp_rxd_parity_error <= 1'b0;
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exp_rxd_data_out <= 8'h00;
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mask_rxd_stop_error <= 1'b0;
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mask_rxd_parity_error <= 1'b0;
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mask_rxd_data_out <= 8'h00;
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end
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io_probe_def
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#(.MESG("uart_host receive error"),
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#(.MESG("uart_host receive error"),
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.WIDTH(8))
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.WIDTH(8))
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rxd_data_out_prb
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rxd_data_out_prb
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(
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(
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.clk ( clk ),
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.clk ( clk ),
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.drive_value (8'bzzzzzzzz ),
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.expected_value ( exp_rxd_data_out ),
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.expected_value ( exp_rxd_data_out ),
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.mask ( mask_rxd_data_out ),
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.mask ( mask_rxd_data_out ),
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.signal ( rxd_data_out )
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.signal ( rxd_data_out )
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Line 121... |
Line 89... |
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io_probe_def
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io_probe_in
|
#(.MESG("uart_host stop error"))
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#(.MESG("uart_host stop error"))
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rxd_stop_error_prb
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rxd_stop_error_prb
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(
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(
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.clk ( clk ),
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.clk ( clk ),
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.drive_value (1'bz ),
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.expected_value ( exp_rxd_stop_error ),
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.expected_value ( exp_rxd_stop_error ),
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.mask ( mask_rxd_stop_error ),
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.mask ( mask_rxd_stop_error ),
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.signal ( rxd_stop_error )
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.signal ( rxd_stop_error )
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);
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);
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io_probe_def
|
io_probe_in
|
#(.MESG("uart_host parity error"))
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#(.MESG("uart_host parity error"))
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rxd_parity_error_prb
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rxd_parity_error_prb
|
(
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(
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.clk ( clk ),
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.clk ( clk ),
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.drive_value (1'bz ),
|
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.expected_value ( exp_rxd_parity_error ),
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.expected_value ( exp_rxd_parity_error ),
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.mask ( mask_rxd_parity_error ),
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.mask ( mask_rxd_parity_error ),
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.signal ( rxd_parity_error )
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.signal ( rxd_parity_error )
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);
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);
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always@(posedge clk)
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if(reset)
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begin
|
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parity_enable <= 1'b0;
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txd_data_in <= 8'h00;
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txd_parity <= 1'b0;
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txd_force_parity <= 1'b0;
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txd_load <= 1'b0;
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txd_break <= 1'b0;
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rxd_parity <= 1'b0;
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rxd_force_parity <= 1'b0;
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rxd_data_avail_stb <= 1'b0;
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exp_rxd_stop_error <= 1'b0;
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exp_rxd_parity_error <= 1'b0;
|
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exp_rxd_data_out <= 8'h00;
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mask_rxd_stop_error <= 1'b0;
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mask_rxd_parity_error <= 1'b0;
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mask_rxd_data_out <= 8'h00;
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end
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endmodule
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endmodule
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