| Line 55... |
Line 55... |
output reg txd_load,
|
output reg txd_load,
|
output reg txd_break,
|
output reg txd_break,
|
output reg rxd_parity,
|
output reg rxd_parity,
|
output reg rxd_force_parity,
|
output reg rxd_force_parity,
|
output reg rxd_data_avail_stb,
|
output reg rxd_data_avail_stb,
|
inout wire [7:0] rxd_data_out,
|
input wire [7:0] rxd_data_out,
|
input wire rxd_data_avail,
|
input wire rxd_data_avail,
|
inout wire rxd_stop_error,
|
input wire rxd_stop_error,
|
inout wire rxd_parity_error
|
input wire rxd_parity_error
|
);
|
);
|
|
|
reg exp_rxd_stop_error;
|
reg exp_rxd_stop_error;
|
reg exp_rxd_parity_error;
|
reg exp_rxd_parity_error;
|
reg [7:0] exp_rxd_data_out;
|
reg [7:0] exp_rxd_data_out;
|
| Line 71... |
Line 71... |
reg mask_rxd_parity_error;
|
reg mask_rxd_parity_error;
|
reg [7:0] mask_rxd_data_out;
|
reg [7:0] mask_rxd_data_out;
|
|
|
|
|
|
|
|
io_probe_in
|
|
|
|
|
|
|
|
|
|
|
always@(posedge clk)
|
|
if(reset)
|
|
begin
|
|
parity_enable <= 1'b0;
|
|
txd_data_in <= 8'h00;
|
|
txd_parity <= 1'b0;
|
|
txd_force_parity <= 1'b0;
|
|
txd_load <= 1'b0;
|
|
txd_break <= 1'b0;
|
|
rxd_parity <= 1'b0;
|
|
rxd_force_parity <= 1'b0;
|
|
rxd_data_avail_stb <= 1'b0;
|
|
exp_rxd_stop_error <= 1'b0;
|
|
exp_rxd_parity_error <= 1'b0;
|
|
exp_rxd_data_out <= 8'h00;
|
|
|
|
mask_rxd_stop_error <= 1'b0;
|
|
mask_rxd_parity_error <= 1'b0;
|
|
mask_rxd_data_out <= 8'h00;
|
|
|
|
|
|
end
|
|
|
|
|
|
|
|
io_probe_def
|
|
#(.MESG("uart_host receive error"),
|
#(.MESG("uart_host receive error"),
|
.WIDTH(8))
|
.WIDTH(8))
|
rxd_data_out_prb
|
rxd_data_out_prb
|
(
|
(
|
.clk ( clk ),
|
.clk ( clk ),
|
.drive_value (8'bzzzzzzzz ),
|
|
.expected_value ( exp_rxd_data_out ),
|
.expected_value ( exp_rxd_data_out ),
|
.mask ( mask_rxd_data_out ),
|
.mask ( mask_rxd_data_out ),
|
.signal ( rxd_data_out )
|
.signal ( rxd_data_out )
|
|
|
|
|
| Line 121... |
Line 89... |
|
|
|
|
|
|
|
|
|
|
io_probe_def
|
io_probe_in
|
#(.MESG("uart_host stop error"))
|
#(.MESG("uart_host stop error"))
|
rxd_stop_error_prb
|
rxd_stop_error_prb
|
(
|
(
|
.clk ( clk ),
|
.clk ( clk ),
|
.drive_value (1'bz ),
|
|
.expected_value ( exp_rxd_stop_error ),
|
.expected_value ( exp_rxd_stop_error ),
|
.mask ( mask_rxd_stop_error ),
|
.mask ( mask_rxd_stop_error ),
|
.signal ( rxd_stop_error )
|
.signal ( rxd_stop_error )
|
|
|
|
|
);
|
);
|
|
|
|
|
|
|
|
|
io_probe_def
|
io_probe_in
|
#(.MESG("uart_host parity error"))
|
#(.MESG("uart_host parity error"))
|
rxd_parity_error_prb
|
rxd_parity_error_prb
|
(
|
(
|
.clk ( clk ),
|
.clk ( clk ),
|
.drive_value (1'bz ),
|
|
.expected_value ( exp_rxd_parity_error ),
|
.expected_value ( exp_rxd_parity_error ),
|
.mask ( mask_rxd_parity_error ),
|
.mask ( mask_rxd_parity_error ),
|
.signal ( rxd_parity_error )
|
.signal ( rxd_parity_error )
|
|
|
|
|
);
|
);
|
|
|
|
|
|
|
|
always@(posedge clk)
|
|
if(reset)
|
|
begin
|
|
parity_enable <= 1'b0;
|
|
txd_data_in <= 8'h00;
|
|
txd_parity <= 1'b0;
|
|
txd_force_parity <= 1'b0;
|
|
txd_load <= 1'b0;
|
|
txd_break <= 1'b0;
|
|
rxd_parity <= 1'b0;
|
|
rxd_force_parity <= 1'b0;
|
|
rxd_data_avail_stb <= 1'b0;
|
|
exp_rxd_stop_error <= 1'b0;
|
|
exp_rxd_parity_error <= 1'b0;
|
|
exp_rxd_data_out <= 8'h00;
|
|
|
|
mask_rxd_stop_error <= 1'b0;
|
|
mask_rxd_parity_error <= 1'b0;
|
|
mask_rxd_data_out <= 8'h00;
|
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
