URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [xml/] [uart_host_def.xml] - Diff between revs 131 and 134

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Rev 131	Rev 134
Line 39...	Line 39...
`uart_host`	`uart_host`
`def default`	`def default`









	`gen_verilog_sim`
	`104.0`
	`none`
	`:Simulation:`
	`./tools/verilog/gen_verilog`


	`destination`
	`uart_host_def`






	`gen_verilog_syn`
	`104.0`
	`none`
	`:Synthesis:`
	`./tools/verilog/gen_verilog`


	`destination`
	`uart_host_def`








`gen_verilogLib_sim`	`gen_verilogLib_sim`
`105.0`	`105.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
Line 78...	Line 115...









`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/top.sim`
`verilogSourcemodule`



`dest_dir../views/sim/`
`verilogSourcelibraryDir`









`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/top.syn`
`verilogSourcemodule`



`dest_dir../views/syn/`
`verilogSourcelibraryDir`














`Hierarchical`	`Hierarchical`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="io_probe"`	`spirit:name="uart_host"`
`spirit:version="def.design"/>`	`spirit:version="def.design"/>`






`sim:Simulation:`	`sim:Simulation:`

`Verilog`	`Verilog`

Line 197...	Line 181...
`wire`	`wire`
`in`	`in`





	`txd_data_in`
	`reg`

	`out`
	`70`




	`rxd_data_out`
	`wire`

	`in`
	`70`






`parity_enable`	`parity_enable`
`reg`	`reg`
`out`	`out`


Line 217...	Line 223...
`txd_buffer_empty`	`txd_buffer_empty`
`wire`	`wire`
`in`	`in`


	`txd_load`
	`reg`
	`out`



	`txd_break`
	`reg`
	`out`



	`rxd_parity`
	`reg`
	`out`



	`rxd_force_parity`
	`reg`
	`out`



	`rxd_data_avail_stb`
	`reg`
	`out`





`rxd_data_avail`	`rxd_data_avail`
`wire`	`wire`
`in`	`in`


Line 234...	Line 272...
`in`	`in`




`output reg [7:0] txd_data_in,`
`output reg txd_load,`
`output reg txd_break,`
`output reg rxd_parity,`
`output reg rxd_force_parity,`
`output reg rxd_data_avail_stb,`
`inout wire [7:0] rxd_data_out,`











	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/code`
	`verilogSourcefragment`





	`../verilog/tasks`
	`verilogSourcefragment`









	`../verilog/sim/uart_host_def`
	`verilogSourcemodule`



	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`









	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/code`
	`verilogSourcefragment`





	`../verilog/syn/uart_host_def`
	`verilogSourcemodule`



	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [xml/] [uart_host_def.xml] - Diff between revs 131 and 134