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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 44...	Line 44...






	`elab_verilog`
	`102.1`
	`none`
	`:Simulation:`
	`./tools/verilog/elab_verilog`


	`dest_dir`
	`io_ports`








`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
Line 263...	Line 279...

`Hierarchical`	`Hierarchical`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="io_probe"`	`spirit:name="uart_model"`
`spirit:version="def.design"/>`	`spirit:version="def.design"/>`



`sim:Simulation:`	`sim:Simulation:`

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