URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 44...	Line 44...






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`








`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.sim`	`uart_model_def`


`dest_dir`
`../verilog`





Line 89...	Line 69...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.syn`	`uart_model_def`


`dest_dir`
`../verilog`














	`Hierarchical`


	`spirit:library="Testbench"`
	`spirit:name="uart_model"`
	`spirit:version="def.design"/>`




	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`







	`sim:Simulation:`

	`Verilog`


	`fs-sim`





	`syn:Synthesis:`

	`Verilog`


	`fs-syn`





	`doc`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="documentation"/>`

	`:Documentation:`
	`Verilog`







	`CLKCNT4'h5`
	`SIZE4`




	`clk`
	`wire`
	`in`


	`reset`
	`wire`
	`in`



	`txd_in`
	`wire`
	`in`


	`rxd_out`
	`wire`
	`out`










`gen_verilogLib_sim`
`105.0`
`none`
`:Simulation:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`sim`





`gen_verilogLib_syn`
`105.0`
`none`
`:Synthesis:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`syn`











`fs-sim`	`fs-sim`



`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/sim/top.out.sim`	`../verilog/top.rtl`
`verilogSourcemodule`	`verilogSourcefragment`





`../verilog/top.rtl`	`../verilog/top.tasks`
`verilogSourcefragment`	`verilogSourcefragment`






`../verilog/top.tasks`	`../verilog/sim/uart_model_def`
`verilogSourcefragment`	`verilogSourcemodule`






`../verilog/serial_rcvr`	`../verilog/serial_rcvr`
`verilogSourcemodule`	`verilogSourcemodule`

Line 214...	Line 259...

`fs-syn`	`fs-syn`



`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`





`../verilog/syn/top.out.syn`	`../verilog/top.rtl`
`verilogSourcemodule`	`verilogSourcefragment`





`../verilog/top.rtl`	`../verilog/serial_rcvr`
`verilogSourcefragment`	`verilogSourcemodule`






`../verilog/serial_rcvr`	`../verilog/syn/uart_model_def`
`verilogSourcemodule`	`verilogSourcemodule`






`../verilog/serial_xmit`	`../verilog/serial_xmit`
`verilogSourcemodule`	`verilogSourcemodule`

Line 271...	Line 320...









`Hierarchical`


`spirit:library="Testbench"`
`spirit:name="uart_model"`
`spirit:version="def.design"/>`



`sim:Simulation:`

`Verilog`


`fs-sim`





`syn:Synthesis:`

`Verilog`


`fs-syn`





`doc`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="documentation"/>`

`:Documentation:`
`Verilog`







`CLKCNT4'h5`
`SIZE4`




`clk`
`wire`
`in`


`reset`
`wire`
`in`



`txd_in`
`wire`
`in`


`rxd_out`
`wire`
`out`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Diff between revs 133 and 134