URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [verilog/] [top.rtl] - Diff between revs 131 and 134

Rev 131	Rev 134
Line 1...	Line 1...


	`assign prb_device_rx_data = 8'h00;`

	`assign prb_device_rx_parity = 1'b0;`

	`always@(posedge clk)`
	`if(reset)`
	`mask_device_rx_parity <= 1'b0;`
	`else`
	`mask_device_rx_parity <= 1'b0;`

	`always@(posedge clk)`
	`if(reset)`
	`mask_device_rx_data <= 8'b0;`
	`else`
	`mask_device_rx_data <= 8'b0;`



`reg [23:0] red_h_cnt;`	`reg [23:0] red_h_cnt;`
`reg [23:0] green_h_cnt;`	`reg [23:0] green_h_cnt;`
Line 82...	Line 97...




`/*`	`/*`
`io_probe_def`	`io_probe_in`
`#(.MESG ("vga data receive error"),`	`#(.MESG ("vga data receive error"),`
`.WIDTH (8)`	`.WIDTH (8)`
`)`	`)`
`rx_shift_buffer_prb`	`rx_shift_buffer_prb`
`(`	`(`
`.clk ( clk ),`	`.clk ( clk ),`
`.drive_value (8'bzzzzzzzz),`
`.expected_value( exp_rx_shift_buffer),`	`.expected_value( exp_rx_shift_buffer),`
`.mask ( mask_rx_shift_buffer),`	`.mask ( mask_rx_shift_buffer),`
`.signal ( prb_rx_shift_buffer)`	`.signal ( prb_rx_shift_buffer)`
`);`	`);`


`io_probe_def`	`io_probe_in`
`#(.MESG ("vga parity error"))`	`#(.MESG ("vga parity error"))`
`rx_parity_err_prb`	`rx_parity_err_prb`
`(`	`(`
`.clk ( clk ),`	`.clk ( clk ),`
`.drive_value (1'bz),`
`.expected_value( exp_rx_parity_err),`	`.expected_value( exp_rx_parity_err),`
`.mask ( mask_rx_parity_err),`	`.mask ( mask_rx_parity_err),`
`.signal ( prb_rx_parity_err)`	`.signal ( prb_rx_parity_err)`
`);`	`);`