URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [xml/] [vga_model_def.xml] - Diff between revs 131 and 134

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 131	Rev 134
Line 54...	Line 54...
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.sim`	`vga_model_def`


`dest_dir`
`../verilog`





Line 73...	Line 69...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.syn`	`vga_model_def`


`dest_dir`
`../verilog`







`gen_verilogLib_sim`
`105.0`
`none`
`:Simulation:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`sim`





`gen_verilogLib_syn`
`105.0`
`none`
`:Synthesis:`
`./tools/verilog/gen_verilogLib`


`dest_dir`
`../views`


`view`
`syn`











`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/sim/top.out.sim`
`verilogSourcemodule`





`../verilog/top.rtl`
`verilogSourcefragment`





`dest_dir../views/sim/`
`verilogSourcelibraryDir`
















`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/syn/top.out.syn`
`verilogSourcemodule`





`../verilog/top.rtl`
`verilogSourcefragment`







`dest_dir../views/syn/`
`verilogSourcelibraryDir`








	`Hierarchical`


	`spirit:library="Testbench"`
	`spirit:name="vga_model"`
	`spirit:version="def.design"/>`





	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`











`Hierarchical`


`spirit:library="Testbench"`
`spirit:name="io_probe"`
`spirit:version="def.design"/>`



`sim:Simulation:`	`sim:Simulation:`

`Verilog`	`Verilog`
Line 323...	Line 213...








	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/sim/vga_model_def`
	`verilogSourcemodule`





	`../verilog/top.rtl`
	`verilogSourcefragment`





	`dest_dir../views/sim/`
	`verilogSourcelibraryDir`
















	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/syn/vga_model_def`
	`verilogSourcemodule`





	`../verilog/top.rtl`
	`verilogSourcefragment`







	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [xml/] [vga_model_def.xml] - Diff between revs 131 and 134