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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [rtl_check.xml] - Diff between revs 134 and 135

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Rev 134 Rev 135
Line 25... Line 25...
//   You should have received a copy of the GNU Lesser General            //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
//                                                                        //
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
Testbench
Testbench
toolflow
toolflow
rtl_check
rtl_check
 
 
 
 
 
 
 
 
 
 
 
 
  gen_filelists
  gen_filelists
  104.0
  104.0
  none
  none
  
  
    :*Lint:*
    :*Lint:*
  
  
  ./tools/sys/gen_child_filelist
  tools/sys/gen_child_filelist
    
    
    
    
      top
      top
    
    
    
    
      top_file
      top_file
      ./TestBench
      ./TestBench
    
    
  
  
 
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
  104.0
  104.0
  none
  none
  :*Lint:*
  :*Lint:*
  ./tools/verilog/gen_verilog
  tools/verilog/gen_verilog
  
  
  
  
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilogLib_lint
  gen_verilogLib_lint
  105.0
  105.0
  none
  none
  :*Lint:*
  :*Lint:*
  ./tools/verilog/gen_verilogLib
  tools/verilog/gen_verilogLib
    
    
    
    
      view
      view
      lint
      lint
    
    
  
  
 
 
 
 
 
 
 
 
 
 
 
  gen_yosys_filelist
 
  104.1
 
  none
 
  
 
    :*Lint:*
 
  
 
  tools/sys/gen_child_filelist
 
  
 
    
 
      suffix
 
      yosys
 
    
 
    
 
      leader
 
      "read_verilog "
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
   
      fs-lint
      fs-lint
 
 
      
      
        dest_dir
        dest_dir
        ../views/lint/
        ../views/lint/
        verilogSource
        verilogSource
        libraryDir
        libraryDir
      
      
 
 
   
   
 
 
 
 
 
 
 
 
 
 
 
 
       
       
 
 
              
              
              lint
              lint
              :*Lint:*
              :*Lint:*
              Verilog
              Verilog
              
              
              fs-lint
              fs-lint
              
              
 
 
      
      
 
 
 
 
 
 
 
 
clk
clk
  wire
  wire
  in
  in
 
 
 
 
reset
reset
  wire
  wire
  in
  in
 
 
 
 
 
 
STOP
STOP
  wire
  wire
  out
  out
 
 
 
 
 
 
BAD
BAD
  wire
  wire
  out
  out
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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