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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilator.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 25...	Line 25...
`// You should have received a copy of the GNU Lesser General //`	`// You should have received a copy of the GNU Lesser General //`
`// Public License along with this source; if not, download it //`	`// Public License along with this source; if not, download it //`
`// from http://www.opencores.org/lgpl.shtml //`	`// from http://www.opencores.org/lgpl.shtml //`
`// //`	`// //`
`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`Testbench`	`Testbench`
`toolflow`	`toolflow`
`verilator`	`verilator`





`gen_filelists`	`gen_filelists`
`104.0`	`104.0`
`none`	`none`

`:Synthesis:`	`:Synthesis:`

`./tools/sys/gen_child_filelist`	`tools/sys/gen_child_filelist`


`top_file`	`top_file`
`"./TestBench"`	`"./TestBench"`


`top`	`top`






`gen_cov_filelist`	`gen_cov_filelist`
`104.0`	`104.0`
`none`	`none`

`:Lint:`	`:Lint:`

`./tools/sys/gen_child_filelist`	`tools/sys/gen_child_filelist`


`top_file`	`top_file`
`"-v ./TestBench"`	`"-v ./TestBench"`


`top`	`top`


`suffix`	`suffix`
`COV`	`COV`


`leader`	`leader`
`"-v "`	`"-v "`










`gen_verilogLib_syn`	`gen_verilogLib_syn`
`105.0`	`105.0`
`none`	`none`
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilogLib`	`tools/verilog/gen_verilogLib`


`view`	`view`
`syn`	`syn`







`gen_verilogLib_lint`	`gen_verilogLib_lint`
`105.0`	`105.0`
`none`	`none`
`:Lint:`	`:Lint:`
`./tools/verilog/gen_verilogLib`	`tools/verilog/gen_verilogLib`


`view`	`view`
`lint`	`lint`


















`fs-syn`	`fs-syn`


`dest_dir`	`dest_dir`
`../views/syn/`	`../views/syn/`
`verilogSource`	`verilogSource`
`libraryDir`	`libraryDir`






`fs-lint`	`fs-lint`


`dest_dir`	`dest_dir`
`../views/lint/`	`../views/lint/`
`verilogSource`	`verilogSource`
`libraryDir`	`libraryDir`






















`PERIOD40`	`PERIOD40`
`TIMEOUT100000`	`TIMEOUT100000`




	`Bfm`





`Bfm`

`spirit:library="Testbench"`
`spirit:name="clock_gen"`
`spirit:version="bfm.design"/>`




`syn`
`:Synthesis:`
`Verilog`

`fs-syn`






`lint`	`Bfm`
`:Lint:`	`Bfm`
`Verilog`

`fs-lint`






	`syn`
	`:Synthesis:`
	`Verilog`

	`fs-syn`






	`lint`
	`:Lint:`
	`Verilog`

	`fs-lint`





`clk`
`wire`
`in`


`START`
`wire`
`in`




`FAIL`
`reg`
`out`



`FINISH`
`reg`
`out`


	`clk`
	`wire`
	`in`


	`START`
	`wire`
	`in`




	`FAIL`
	`reg`
	`out`



	`FINISH`
	`reg`
	`out`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilator.xml] - Diff between revs 134 and 135