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https://opencores.org/ocsvn/socgen/socgen/trunk
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| Rev 131 |
Rev 135 |
| Line 1... |
Line 1... |
v 20121203 2
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v 20100214 1
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C 1600 4300 1 0 0 in_port.sym
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C 1400 300 1 0 0 in_port.sym
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{
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{
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T 2100 4100 5 10 1 1 0 6 1
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T 1400 300 5 10 1 1 0 6 1 1
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refdes=enable
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refdes=enable
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}
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}
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C 1600 2800 1 0 0 in_port.sym
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C 1400 700 1 0 0 in_port.sym
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{
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{
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T 1900 2600 5 10 1 1 0 6 1
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T 1400 700 5 10 1 1 0 6 1 1
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refdes=clk_in
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refdes=clk_in
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}
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}
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C 1600 4700 1 0 0 in_port.sym
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C 1400 1100 1 0 0 in_port.sym
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{
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{
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T 2300 5100 5 10 1 1 0 6 1
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T 1400 1100 5 10 1 1 0 6 1 1
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refdes=atg_clk_mode
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refdes=atg_clk_mode
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}
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}
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C 8200 4300 1 0 0 out_port.sym
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C 3400 300 1 0 0 out_port.sym
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{
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{
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T 9200 4300 5 10 1 1 0 0 1
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T 4400 300 5 10 1 1 0 0 1 1
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refdes=clk_out
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refdes=clk_out
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}
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}
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C 4500 3000 1 0 0 latch.sym
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{
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T 6300 4800 5 10 0 0 0 0 1
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device=LATCH
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T 5800 5000 5 10 1 1 0 6 1
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refdes=U?
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}
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C 6700 4100 1 0 0 and2-1.sym
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{
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T 7100 4000 5 10 1 1 0 2 1
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refdes=U?
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T 7100 4200 5 8 0 0 0 0 1
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device=and
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}
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C 3000 3100 1 0 0 not-1.sym
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{
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T 3200 4100 5 10 0 0 0 0 1
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device=not
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T 3500 3400 5 10 1 1 0 2 1
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refdes=U?
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}
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N 8200 4400 8000 4400 4
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N 4100 3600 4500 3600 4
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N 2500 2900 6700 2900 4
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N 6700 4600 6100 4600 4
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N 3000 3600 3000 2900 4
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C 3000 4300 1 0 0 or2-1.sym
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{
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T 3400 4200 5 10 1 1 0 2 1
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refdes=U?
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T 3400 4400 5 8 0 0 0 0 1
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device=or
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}
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N 3000 4400 2500 4400 4
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N 3000 4800 2500 4800 4
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N 4500 4600 4300 4600 4
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N 6700 4200 6700 2900 4
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