URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_sys.v] - Diff between revs 131 and 134

Rev 131	Rev 134
Line 31...	Line 31...

`(`	`(`
`input wire a_clk_pad_in,`	`input wire a_clk_pad_in,`
`input wire b_clk_pad_in,`	`input wire b_clk_pad_in,`
`input wire pwron_pad_in,`	`input wire pwron_pad_in,`


`output wire div_clk_out,`	`output wire div_clk_out,`

`output reg one_usec,`	`output reg one_usec,`
`output wire reset`	`output wire reset`

`);`	`);`

`wire ckIn;`	`wire ckIn;`
`wire dll_clk;`	`wire dll_clk;`

`reg ref_reset;`	`reg ref_reset;`

`reg [6:0] counter;`	`reg [6:0] counter;`
`reg [3:0] reset_cnt;`	`reg [3:0] reset_cnt;`

`wire pwron_reset;`	`wire pwron_reset;`
	`wire pwron_reset_n;`
`wire dll_reset;`	`wire dll_reset;`

	`assign pwron_reset_n = !pwron_reset;`



`generate`	`generate`

`if( CLOCK_SRC)`	`if( CLOCK_SRC)`

Line 142...	Line 142...
`.DEPTH (2),`	`.DEPTH (2),`
`.RST_VAL(1'b1)`	`.RST_VAL(1'b1)`
`)`	`)`
`ref_rsync(`	`ref_rsync(`
`.clk (div_clk_out),`	`.clk (div_clk_out),`
`.reset_n (!pwron_reset),`	`.reset_n (pwron_reset_n),`
`.data_in (ref_reset),`	`.data_in (ref_reset),`
`.data_out (reset)`	`.data_out (reset)`
`);`	`);`


Line 155...	Line 155...
`.DEPTH (2),`	`.DEPTH (2),`
`.RST_VAL(1'b1)`	`.RST_VAL(1'b1)`
`)`	`)`
`dll_rsync(`	`dll_rsync(`
`.clk (dll_clk),`	`.clk (dll_clk),`
`.reset_n (!pwron_reset),`	`.reset_n (pwron_reset_n),`
`.data_in (ref_reset),`	`.data_in (ref_reset),`
`.data_out (dll_reset)`	`.data_out (dll_reset)`
`);`	`);`