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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_dll.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 1...	Line 1...



`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`cde`	`cde`
`clock`	`clock`
`dll default`	`dll`






	`ref_clk`






	`clk`
	`ref_clk`








	`dll_clk_out`






	`clk`
	`dll_clk_out`








`gen_verilog_sim`
`104.0`
`none`
`:Simulation:`
`./tools/verilog/gen_verilog`


`destination`
`clock_dll`





	`reset`
`gen_verilog_sim`
`104.0`
`none`
`:Synthesis:`
`./tools/verilog/gen_verilog`

	`reset`
`destination`	`reset`
`clock_dll`


















	`gen_verilog_sim`
	`104.0`
	`none`
	`:Simulation:`
	`tools/verilog/gen_verilog`


	`destination`
	`clock_dll`






	`gen_verilog_syn`
	`104.0`
	`none`
	`:Synthesis:`
	`tools/verilog/gen_verilog`


	`destination`
	`clock_dll`












`verilog`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`







`sim:Simulation:`

`Verilog`


`fs-sim`




`syn:Synthesis:`

`Verilog`


`fs-syn`




`doc`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="documentation"/>`

`:Documentation:`
`Verilog`







	`verilog`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="verilog"/>`






`DIV4`
`MULT2`
`SIZE4`



	`sim:Simulation:`

`ref_clk`	`Verilog`
`wire`
`in`
	`fs-sim`




	`syn:Synthesis:`

`reset`	`Verilog`
`wire`
`in`
	`fs-syn`



`dll_clk_out`
`reg`	`doc`
`out`

	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`


`div_clk_out`
`reg`
`out`










	`DIV4`
	`MULT2`
	`SIZE4`




	`ref_clk`
	`wire`
	`in`



	`reset`
	`wire`
	`in`


	`dll_clk_out`
`fs-sim`	`reg`
	`out`


	`div_clk_out`
	`reg`
`../verilog/copyright`	`out`
`verilogSourceinclude`




`../verilog/timescale`
`verilogSourceinclude`




`../verilog/sim/dll`
`verilogSourcefragment`




`../verilog/sim/clock_dll`
`verilogSourcemodule`







`dest_dir`
`../views/sim/`
`verilogSourcelibraryDir`







`fs-syn`	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/timescale`
	`verilogSourceinclude`




	`../verilog/sim/dll`
	`verilogSourcefragment`




`../verilog/copyright`	`../verilog/sim/clock_dll`
`verilogSourceinclude`	`verilogSourcemodule`






`../verilog/syn/dll`
`verilogSourcefragment`



	`dest_dir`
`../verilog/syn/clock_dll`	`../views/sim/`
`verilogSourcemodule`	`verilogSourcelibraryDir`






`dest_dir`	`fs-syn`
`../views/syn/`
`verilogSourcelibraryDir`








	`../verilog/copyright`
	`verilogSourceinclude`




`fs-lint`

`dest_dir../views/syn/`
`verilogSourcelibraryDir`




	`../verilog/syn/dll`
	`verilogSourcefragment`




	`../verilog/syn/clock_dll`
	`verilogSourcemodule`





	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`










	`fs-lint`

	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_dll.xml] - Diff between revs 134 and 135