URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_dll.xml] - Diff between revs 131 and 134

Rev 131	Rev 134
Line 1...	Line 1...



`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
Line 20...	Line 20...






	`gen_verilog_sim`
	`104.0`
	`none`
	`:Simulation:`
	`./tools/verilog/gen_verilog`


	`destination`
	`clock_dll`






	`gen_verilog_sim`
	`104.0`
	`none`
	`:Synthesis:`
	`./tools/verilog/gen_verilog`


	`destination`
	`clock_dll`













`fs-sim`



`dest_dir`
`../verilog/sim/`
`verilogSourcelibraryDir`






`fs-syn`


`dest_dir`
`../verilog/syn/`
`verilogSourcelibraryDir`









`fs-lint`

`dest_dir../verilog/syn/`
`verilogSourcelibraryDir`














	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`









`sim:Simulation:`	`sim:Simulation:`

`Verilog`	`Verilog`
Line 133...	Line 133...
`wire`	`wire`
`in`	`in`



`dll_clk_out`
`wire`
`out`



`reset`	`reset`
`wire`	`wire`
`in`	`in`


	`dll_clk_out`
	`reg`
	`out`


`div_clk_out`	`div_clk_out`
`reg`	`reg`
`out`	`out`

Line 160...	Line 156...










	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/timescale`
	`verilogSourceinclude`




	`../verilog/sim/dll`
	`verilogSourcefragment`




	`../verilog/sim/clock_dll`
	`verilogSourcemodule`






	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`






	`fs-syn`






	`../verilog/copyright`
	`verilogSourceinclude`






	`../verilog/syn/dll`
	`verilogSourcefragment`




	`../verilog/syn/clock_dll`
	`verilogSourcemodule`





	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`









	`fs-lint`

	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`