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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 1...	Line 1...



`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`cde`	`cde`
`clock`	`clock`
`sys default`	`sys`






`clock`	`clock`





`clk`
`div_clk_out`	`clk`
	`div_clk_out`








`reset`	`reset`





`reset`
`reset`	`reset`
	`reset`














`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`:common:`
`./tools/verilog/gen_verilog`	`tools/verilog/gen_verilog`


`destination`	`destination`
`clock_sys`	`clock_sys`



















`Hierarchical`
	`Hierarchical`





`spirit:library="cde"`
`spirit:name="clock"`
`spirit:version="sys.design"/>`



`verilog`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`






`commoncommon`
`Verilog`


`fs-common`




	`Hierarchical`
	`Hierarchical`



	`verilog`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="verilog"/>`





`sim:Simulation:`
`Verilog`


`fs-sim`




`syn:Synthesis:`	`common:common:`
`Verilog`	`Verilog`


`fs-syn`	`fs-common`




`doc`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="documentation"/>`

`:Documentation:`
`Verilog`





	`sim:Simulation:`
	`Verilog`


	`fs-sim`




	`syn:Synthesis:`
	`Verilog`


	`fs-syn`




	`doc`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`







`FREQ48`
`PLL_MULT2`
`PLL_DIV4`
`PLL_SIZE4`
`CLOCK_SRC0`
`RESET_SENSE0`




`a_clk_pad_in`
`wire`
`in`


`b_clk_pad_in`
`wire`
`in`


`pwron_pad_in`
`wire`
`in`


`div_clk_out`
`wire`	`FREQ48`
`out`	`PLL_MULT2`
	`PLL_DIV4`
	`PLL_SIZE4`
	`CLOCK_SRC0`
	`RESET_SENSE0`


`one_usec`
`reg`
`out`


`reset`	`a_clk_pad_in`
`wire`	`wire`
`out`	`in`


	`b_clk_pad_in`
	`wire`
	`in`


	`pwron_pad_in`
	`wire`
	`in`


	`div_clk_out`
	`wire`
	`out`


	`one_usec`
	`reg`
	`out`


	`reset`
	`wire`
	`out`














`fs-common`



`../verilog/clock_sys`
`verilogSourcefragment`






`fs-sim`


	`fs-common`
`../verilog/copyright`
`verilogSourceinclude`




	`../verilog/clock_sys`
	`verilogSourcefragment`




`../verilog/common/clock_sys`
`verilogSourcemodule`




`dest_dir`	`fs-sim`
`../views/sim/`
`verilogSource`
`libraryDir`




	`../verilog/copyright`
	`verilogSourceinclude`




`fs-syn`
	`../verilog/common/clock_sys`
	`verilogSourcemodule`




	`dest_dir`
`../verilog/copyright`	`../views/sim/`
`verilogSourceinclude`	`verilogSource`
	`libraryDir`






`../verilog/common/clock_sys`
`verilogSourcemodule`



	`fs-syn`


`dest_dir`
`../views/syn/`
`verilogSource`
`libraryDir`




	`../verilog/copyright`
	`verilogSourceinclude`





	`../verilog/common/clock_sys`
	`verilogSourcemodule`




`fs-lint`
	`dest_dir`
`dest_dir`	`../views/syn/`
`../views/syn/`	`verilogSource`
`verilogSourcelibraryDir`	`libraryDir`









	`fs-lint`

	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Diff between revs 134 and 135