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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Diff between revs 131 and 134

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Rev 131	Rev 134
Line 14...	Line 14...
`clock`	`clock`
`sys default`	`sys default`

















`clock`	`clock`

Line 56...	Line 45...









	`gen_verilog`
	`104.0`
	`none`
	`common`
	`./tools/verilog/gen_verilog`


	`destination`
	`clock_sys`


















Line 71...	Line 86...
`spirit:name="clock"`	`spirit:name="clock"`
`spirit:version="sys.design"/>`	`spirit:version="sys.design"/>`



	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`






	`commoncommon`
	`Verilog`


	`fs-common`







`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`


`fs-sim`	`fs-sim`
Line 136...	Line 175...
`wire`	`wire`
`in`	`in`


`div_clk_out`	`div_clk_out`
`reg`	`wire`
`out`	`out`


`one_usec`	`one_usec`
`reg`	`reg`
Line 162...	Line 201...










	`fs-common`



	`../verilog/clock_sys`
	`verilogSourcefragment`






`fs-sim`	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`





	`../verilog/common/clock_sys`
	`verilogSourcemodule`




`dest_dir`	`dest_dir`
`../verilog/`	`../views/sim/`
`verilogSource`	`verilogSource`
`libraryDir`	`libraryDir`






`fs-syn`	`fs-syn`




	`../verilog/copyright`
	`verilogSourceinclude`





	`../verilog/common/clock_sys`
	`verilogSourcemodule`




`dest_dir`	`dest_dir`
`../verilog/`	`../views/syn/`
`verilogSource`	`verilogSource`
`libraryDir`	`libraryDir`



Line 195...	Line 278...


`fs-lint`	`fs-lint`

`dest_dir`	`dest_dir`
`../verilog/`	`../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`

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