OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [xml/] [cde_divider_def.xml] - Diff between revs 131 and 134

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 131 Rev 134
Line 20... Line 20...
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
 
  104.0
 
  none
 
  common
 
  ./tools/verilog/gen_verilog
 
  
 
    
 
      destination
 
      divider_def
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-sim
 
 
 
 
 
      
 
        dest_dir
 
        ../verilog/
 
        verilogSourcelibraryDir
 
      
 
 
 
  
 
 
 
 
 
   
 
      fs-syn
 
 
 
      
 
        dest_dir
 
        ../verilog/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
   
 
 
 
 
 
    
 
 
 
      fs-lint
 
      
 
        dest_dir
 
        ../verilog/
 
        verilogSourcelibraryDir
 
      
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
       
       
 
              
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
 
 
 
              
              
 
              commoncommon
 
              Verilog
 
              
 
                     
 
                            fs-common
 
                     
 
              
 
 
 
 
 
              
              sim:*Simulation:*
              sim:*Simulation:*
              Verilog
              Verilog
              
              
                     
                     
                            fs-sim
                            fs-sim
Line 168... Line 155...
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/divider_def
 
        verilogSourcefragment
 
      
 
 
 
    
 
 
 
 
 
   
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/common/divider_def
 
        verilogSourcemodule
 
      
 
 
 
       
 
        dest_dir
 
        ../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
  
 
 
 
 
 
   
 
      fs-syn
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
     
 
        
 
        ../verilog/common/divider_def
 
        verilogSourcemodule
 
      
 
 
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
   
 
 
 
 
 
 
 
 
 
    
 
 
 
      fs-lint
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.