URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_in_reg.xml] - Diff between revs 131 and 134

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 131	Rev 134
Line 12...	Line 12...
`opencores.org`	`opencores.org`
`cde`	`cde`
`jtag`	`jtag`
`classic_rpc_in_reg default`	`classic_rpc_in_reg default`











	`jtag`





	`test_logic_reset`
	`test_logic_reset`



	`capture_dr`
	`capture_dr`



`fs-sim`	`shift_dr`
	`shift_dr`



	`update_dr_clk`
	`update_dr_clk`



`dest_dir`
`../verilog/`
`verilogSourcelibraryDir`



	`tdi`
	`tdi`



	`tdo`
	`tdo`



`fs-syn`	`select`
	`select`



`dest_dir`
`../verilog/`
`verilogSourcelibraryDir`



	`shiftcapture_dr_clk`
	`shiftcapture_dr_clk`










`fs-lint`

`dest_dir../verilog/`
`verilogSourcelibraryDir`

























	`gen_verilog`
	`104.0`
	`none`
	`common`
	`./tools/verilog/gen_verilog`


	`destination`
	`jtag_classic_rpc_in_reg`













Line 76...	Line 125...





	`verilog`


	`spirit:library="Testbench"`
	`spirit:name="toolflow"`
	`spirit:version="verilog"/>`






	`commoncommon`
	`Verilog`


	`fs-common`







`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`


`fs-sim`	`fs-sim`
Line 116...	Line 189...






`BITS16`
`RESET_VALUE'h0`




`shiftcapture_dr_clk`
`wire`
`in`


`test_logic_reset`
`wire`	`fs-common`
`in`




	`../verilog/classic_rpc_in_reg`
	`verilogSourcefragment`


`tdi`
`wire`
`in`


`select`
`wire`
`in`	`../verilog/copyright`
	`verilogSourceinclude`


`capture_dr`
`wire`
`in`


`shift_dr`
`wire`
`in`




`tdo`
`wire`
`out`



	`fs-sim`




	`../verilog/common/jtag_classic_rpc_in_reg`
	`verilogSourcemodule`




	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`






	`fs-syn`



	`../verilog/common/jtag_classic_rpc_in_reg`
	`verilogSourcemodule`




	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`









	`fs-lint`





	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

















	`BITS16`
	`RESET_VALUE'h0`





`capture_value`	`capture_value`
`wire`	`wire`
`in`	`in`

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_in_reg.xml] - Diff between revs 131 and 134